Patents by Inventor Hiroyasu Kitajima
Hiroyasu Kitajima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10032785Abstract: A pair of floating gates disposed to be spaced apart from each other by a first distance and a pair of spacer insulating films disposed on each of the pair of floating gates are provided in a memory region. Also, a pair of floating gates disposed to be spaced apart from each other by a second distance and a pair of spacer insulating films disposed on each of the pair of floating gates are provided in a monitor region. Then, the second distance is smaller than the first distance. Thus, by narrowing a distance between the floating gates in the monitor region, a tapered portion can be provided on a side surface portion of the floating gate in the monitor region. Then, by checking this tapered portion, it is possible to understand the shape of the floating gate in the memory region.Type: GrantFiled: August 26, 2016Date of Patent: July 24, 2018Assignee: Renesas Electronics CorporationInventor: Hiroyasu Kitajima
-
Patent number: 9920460Abstract: A down-proof woven fabric includes a cloth composed of synthetic fibers with a yarn fineness of 33 decitex or less and having a weight per unit area of 50 g/m2 or less and a cover factor of 1,400 to 1,800, wherein the cloth is coated at least on one surface thereof with a resin by an amount of 0.1 g/m2 to 5 g/m2 as a solid component.Type: GrantFiled: June 17, 2010Date of Patent: March 20, 2018Assignee: Toray Industries, Inc.Inventors: Tsunemitsu Kitagawa, Shintaro Kazahaya, Hiroyasu Kitajima
-
Publication number: 20170062448Abstract: A pair of floating gates disposed to be spaced apart from each other by a first distance and a pair of spacer insulating films disposed on each of the pair of floating gates are provided in a memory region. Also, a pair of floating gates disposed to be spaced apart from each other by a second distance and a pair of spacer insulating films disposed on each of the pair of floating gates are provided in a monitor region. Then, the second distance is smaller than the first distance. Thus, by narrowing a distance between the floating gates in the monitor region, a tapered portion can be provided on a side surface portion of the floating gate in the monitor region. Then, by checking this tapered portion, it is possible to understand the shape of the floating gate in the memory region.Type: ApplicationFiled: August 26, 2016Publication date: March 2, 2017Applicant: Renesas Electronics CorporationInventor: Hiroyasu KITAJIMA
-
Patent number: 9559063Abstract: A semiconductor device includes an interlayer insulating layer disposed over a semiconductor substrate, and including a plurality of wiring layers; a seal ring disposed in the interlayer insulating layer, and surrounding a circuit region of the semiconductor substrate; a crack lead ring disposed in the interlayer insulating layer, and surrounding the seal ring; and a protective film disposed over the interlayer insulating layer, and covering the crack lead ring and the seal ring. The crack lead ring includes an uppermost wiring layer in an uppermost layer of a plurality of wiring layers. When the crack lead ring has a wiring in an underlayer below the uppermost layer, the uppermost layer wiring extends towards the outside of the device, relative to the wiring in the underlayer. The protective film has an end overlapped with an end of the uppermost layer wiring to form a step over the interlayer insulating layer.Type: GrantFiled: July 19, 2013Date of Patent: January 31, 2017Assignee: Renesas Electronics CorporationInventors: Takeshi Watanabe, Junya Ishii, Hirofumi Saitou, Hiroyasu Kitajima, Tatsuki Kojima, Yoshitsugu Kawashima
-
Publication number: 20140027928Abstract: A semiconductor device an interlayer insulating layer disposed over a semiconductor substrate, and including a plurality of wiring layers; a seal ring disposed in the interlayer insulating layer, and surrounding a circuit region of the semiconductor substrate; a crack lead ring disposed in the interlayer insulating layer, and surrounding the seal ring; and a protective film disposed over the interlayer insulating layer, and covering the crack lead ring and the seal ring. The crack lead ring includes an uppermost wiring layer in an uppermost layer of a plurality of wiring layers. When the crack lead ring has a wiring in an underlayer below the uppermost layer, the uppermost layer wiring extends towards the outside of the device, relative to the wiring in the underlayer. The protective film has an end overlapped with an end of the uppermost layer wiring to form a step over the interlayer insulating layer.Type: ApplicationFiled: July 19, 2013Publication date: January 30, 2014Inventors: Takeshi WATANABE, Junya ISHII, Hirofumi SAITOU, Hiroyasu KITAJIMA, Tatsuki KOJIMA, Yoshitsugu KAWASHIMA
-
Publication number: 20120183754Abstract: A down-proof woven fabric includes a cloth composed of synthetic fibers with a yarn fineness of 33 decitex or less and having a weight per unit area of 50 g/m2 or less and a cover factor of 1,400 to 1,800, wherein the cloth is coated at least on one surface thereof with a resin by an amount of 0.1 g/m2 to 5 g/m2 as a solid component.Type: ApplicationFiled: June 17, 2010Publication date: July 19, 2012Applicant: TORAY INDUSTRIES, INC.Inventors: Tsunemitsu Kitagawa, Shintaro Kazahaya, Hiroyasu Kitajima
-
Publication number: 20110079834Abstract: A semiconductor integrated circuit device has: a MISFET having source/drain diffusion layers; first plugs respectively connected to the source/drain diffusion layers; a first interconnection connected to one of the source/drain diffusion layers through the first plug; a second plug electrically connected to the other Of the source/drain diffusion layers through the first plug; a second interconnection connected to the second plug; and a capacitor electrode located above a gate electrode of the MISFET. The first interconnection is formed not above the lower capacitor electrode, while the second interconnection is formed above the upper capacitor electrode. A plug connecting the first interconnection and another interconnection is not provided at an upper location of the one of the source/drain diffusion layers. The first interconnection is not provided at an upper location of the other of the source/drain diffusion layers.Type: ApplicationFiled: October 1, 2010Publication date: April 7, 2011Applicant: Renesas Electronics CorporationInventors: Masayuki YANAGISAWA, Hiroshi Furuta, Hiroyasu Kitajima, Katsuya Izumi
-
Patent number: 7772070Abstract: A semiconductor integrated circuit device according to an embodiment of the present invention includes a functional circuit region including a functional circuit, a dummy region formed in a region other than the functional circuit region, and plural dummy MOSFETs formed in a dummy region and having a dummy gate electrode on a dummy diffusion layer, the plural dummy MOSFETs being arranged such that date rates of the dummy diffusion layer and dummy gate electrode are kept constant in a predetermined section.Type: GrantFiled: February 28, 2007Date of Patent: August 10, 2010Assignee: NEC Electronics CorporationInventors: Hiroyasu Kitajima, Hiroshi Furuta, Toshikatsu Jinbo
-
Publication number: 20100032740Abstract: A semiconductor device that enables placement of a line or the like under a fuse without any additional step and a method of manufacturing the same are provided. The semiconductor device includes a plurality of first capacitor holes made in an insulating layer, a capacitor formed in the first capacitor holes, a DRAM cell made up of the capacitor and a transistor coupled to the capacitor, a plurality of second capacitor holes made in the insulating layer, and a fuse formed between the second capacitor holes.Type: ApplicationFiled: July 8, 2009Publication date: February 11, 2010Applicant: NEC ELECTRONICS CORPORATIONInventor: Hiroyasu Kitajima
-
Patent number: 7298002Abstract: A semiconductor device includes cylindrical capacitors each including corresponding cylindrical electrodes. Each cylindrical electrode includes hemispherical silicon grains. The hemispherical silicon grains protruding from an upper region of the cylindrical electrode have a large size, and the hemispherical silicon grains protruding from a lower region of the cylindrical electrode have a small size or the lower region of the cylindrical electrode has no hemispherical silicon grains.Type: GrantFiled: June 24, 2005Date of Patent: November 20, 2007Assignee: Elpida Memory Inc.Inventors: Hiroyuki Kitamura, Yuki Togashi, Hiroyasu Kitajima, Noriaki Ikeda, Yoshitaka Nakamura, Eiichiro Kakehashi
-
Publication number: 20070221957Abstract: A semiconductor integrated circuit device according to an embodiment of the present invention includes a functional circuit region including a functional circuit, a dummy region formed in a region other than the functional circuit region, and plural dummy MOSFETs formed in a dummy region and having a dummy gate electrode on a dummy diffusion layer 12, the plural dummy MOSFETs being arranged such that date rates of the dummy diffusion layer and dummy gate electrode are kept constant in a predetermined section.Type: ApplicationFiled: February 28, 2007Publication date: September 27, 2007Inventors: Hiroyasu Kitajima, Hiroshi Furuta, Toshikatsu Jinbo
-
Publication number: 20060022251Abstract: A semiconductor device includes cylindrical capacitors each including corresponding cylindrical electrodes. Each cylindrical electrode includes hemispherical silicon grains. The hemispherical silicon grains protruding from an upper region of the cylindrical electrode have a large size, and the hemispherical silicon grains protruding from a lower region of the cylindrical electrode have a small size or the lower region of the cylindrical electrode has no hemispherical silicon grains.Type: ApplicationFiled: June 24, 2005Publication date: February 2, 2006Inventors: Hiroyuki Kitamura, Yuki Togashi, Hiroyasu Kitajima, Noriaki Ikeda, Yoshitaka Nakamura, Eiichiro Kakehashi