Abstract: A semiconductor device capable of performing sufficient power supply while suppressing an increase in a manufacturing cost. The semiconductor device has a semiconductor substrate, a multilayer interconnection layer provided over the semiconductor substrate, an Al wiring layer that is provided over the multilayer interconnection layer and has pad parts, and a redistribution layer that is provided over the Al wiring layer and is coupled with the Al wiring layer, in which the redistribution layer is comprised of a metal material whose electric resistivity is lower than that of Al and is not formed over the pad parts.

Abstract: A semiconductor device, in which it is possible to maintain high reliability in that interfacial breakdown does not occur between a solder ball and a conductive film, is provided. The semiconductor device according to the present invention comprises an uppermost layer interconnection 101, an insulating film, which is provided above the uppermost layer interconnection 101, provided with a pad via 104 reaching the uppermost layer interconnection 101, and a conductive film, which is connected to the uppermost layer interconnection 101 in a bottom of the pad via 104, and formed across from the bottom of the pad via 104 to outside the pad via 104; wherein the conductive film and the solder ball 108 provided in contact with the insulating film, and an alloy layer 110 containing a metallic element contained in the solder ball 108 and a metallic element contained in the conductive film intervene, and the solder ball is formed so as to cover the alloy layer 110.

Abstract: A semiconductor device, which is capable of suppressing interfacial breakdown between a solder ball and a conductive film, is provided. The semiconductor device of the present invention, when “a” is distance between a terminal part of the solder ball 108 in a face coming into contact with an insulating resin layer 105 and an upper periphery of a via 104, and “b” is distance between a terminal part of the UBM film 107 and the upper periphery of the via 104, the semiconductor device is made to fulfill with 0<a/b?2.

Abstract: There is provided a technique for obtaining improved maximum allowed value for the antenna ratio while inhibiting the damage on the gate insulating film of the MOSFET. A semiconductor device having a configuration that comprises a silicon substrate, a contact interlayer film, a first interconnect interlayer film, a first via interlayer film and a second interconnect interlayer film, all of which are sequentially formed in this order, comprises two protective diodes, which are coupled to a MOSFET via the second interconnect.

Abstract: In a provided semiconductor device, a plurality of seal rings each made of a conductive material is formed along a periphery of the semiconductor chip and as to surround the circuit formation portion, the seal rings being connected with the semiconductor substrate and being buried in the plurality of wiring insulating films in such a manner as to extend over the wiring insulating films, and one or more slit-like notches are formed at specified positions in the plurality of seal rings in such a manner that the respective slit-like notches in two seal rings being adjacent to each other are not aligned.

Abstract: A semiconductor device, in which it is possible to maintain high reliability in that interfacial breakdown does not occur between a solder ball and a conductive film, is provided. The semiconductor device according to the present invention comprises an uppermost layer interconnection 101, an insulating film, which is provided above the uppermost layer interconnection 101, provided with a pad via 104 reaching the uppermost layer interconnection 101, and a conductive film, which is connected to the uppermost layer interconnection 101 in a bottom of the pad via 104, and formed across from the bottom of the pad via 104 to outside the pad via 104; wherein the conductive film and the solder ball 108 provided in contact with the insulating film, and an alloy layer 110 containing a metallic element contained in the solder ball 108 and a metallic element contained in the conductive film intervene, and the solder ball is formed so as to cover the alloy layer 110.

Abstract: A semiconductor device, which is capable of suppressing interfacial breakdown between a solder ball and a conductive film, is provided. The semiconductor device of the present invention, when “a” is distance between a terminal part of the solder ball 108 in a face coming into contact with an insulating resin layer 105 and an upper periphery of a via 104, and “b” is distance between a terminal part of the UBM film 107 and the upper periphery of the via 104, the semiconductor device is made to fulfill with 0<a/b?2.

Abstract: There is provided a technique for obtaining improved maximum allowed value for the antenna ratio while inhibiting the damage on the gate insulating film of the MOSFET. A semiconductor device having a configuration that comprises a silicon substrate, a contact interlayer film, a first interconnect interlayer film, a first via interlayer film and a second interconnect interlayer film, all of which are sequentially formed in this order, comprises two protective diodes, which are coupled to a MOSFET via the second interconnect.

Abstract: In a provided semiconductor device, a plurality of seal rings each made of a conductive material is formed along a periphery of the semiconductor chip and as to surround the circuit formation portion, the seal rings being connected with the semiconductor substrate and being buried in the plurality of wiring insulating films in such a manner as to extend over the wiring insulating films, and one or more slit-like notches are formed at specified positions in the plurality of seal rings in such a manner that the respective slit-like notches in two seal rings being adjacent to each other are not aligned.

Abstract: In a mixed-loaded type semiconductor device including a plurality of MOS transistors having gate insulating films different in thickness, the antenna standard for the MOS transistor having the gate insulating film with a thickness equal to or smaller than a predetermined thickness is relaxed compared with that for the MOS transistor having the gate insulating film with a thickness larger than the predetermined thickness. In particular, the antenna standard for the MOS transistor having the gate insulating film with a thickness equal to or smaller than 2.6 nm allowing the tunneling of the electric charges to occur is relaxed compared with that for the MOS transistor having the gate insulating film with a thickness larger than 2.6 nm.