Patents by Inventor Hiroyasu Nishimura

Hiroyasu Nishimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8107116
    Abstract: An image processing apparatus comprises a memory; a store control section to divide and store image data in plural vacant memory regions in the memory; and an image administrating information registering section to register each divided image data divided by the store control section by correlating position information of each divided image data in the image data before dividing the image data with storing position information of each divided image data indicating a storing memory region.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: January 31, 2012
    Assignee: Konica Minolta Business Technologies, Inc.
    Inventors: Munetoshi Eguchi, Tomohiro Suzuki, Yuji Tamura, Tetsuya Ishikawa, Hiroyasu Nishimura, Tomoya Ogawa, Fumikage Uchida, Nao Moromizato, Masayuki Yasukaga
  • Patent number: 8060781
    Abstract: A data processing apparatus which saves data in a volatile memory into a nonvolatile memory when power is off, the data processing apparatus including: a detecting circuit for outputting a momentary interruption detecting signal when a power source voltage is below a first threshold voltage, and a power failure detecting signal when the power source voltage is below a second threshold voltage that is lower than the first threshold voltage; and a control section adapted to start saving of the data in the volatile memory into the nonvolatile memory when the detecting circuit has output the momentary interruption detecting signal, continue save of the data, and carry out a predetermined shutdown processing when the detecting circuit has output the power failure detecting signal after the detecting circuit has output the momentary interruption detecting signal.
    Type: Grant
    Filed: October 3, 2007
    Date of Patent: November 15, 2011
    Assignee: Konica Minolta Business Technologies, Inc.
    Inventors: Tetsuya Ishikawa, Tomohiro Suzuki, Yuji Tamura, Hiroyasu Nishimura, Tomoya Ogawa, Fumikage Uchida, Nao Moromizato, Munetoshi Eguchi, Kenji Okuyama
  • Patent number: 7861040
    Abstract: A memory apparatus including: a cache control section to control a cache memory for an auxiliary storage apparatus; a volatile memory; and a nonvolatile memory, wherein the cache memory for the auxiliary storage apparatus is configured to have a volatile cache memory provided in the volatile memory and a nonvolatile cache memory provided in the nonvolatile memory, and wherein the cache control section accesses the nonvolatile cache memory using a write back method.
    Type: Grant
    Filed: November 15, 2007
    Date of Patent: December 28, 2010
    Assignee: Konica Minolta Business Technologies, Inc.
    Inventors: Kenji Okuyama, Tomohiro Suzuki, Yuji Tamura, Tetsuya Ishikawa, Hiroyasu Nishimura, Tomoya Ogawa, Fumikage Uchida, Nao Moromizato, Munetoshi Eguchi
  • Patent number: 7707376
    Abstract: An information processing apparatus including: a nonvolatile memory; a volatile system memory in which predetermined data stored in the nonvolatile memory is developed; a control section to save the predetermined data stored in the system memory in the nonvolatile memory when a start of power-off operation is detected; and a storage section that stores a first timing information representing a time point of terminating the operation of saving the predetermined data in the nonvolatile memory, and a second timing information representing a power-off time point, wherein the control section compares the first timing information stored in the storage section with the second timing information, subsequent to the next operation of turning on of the power.
    Type: Grant
    Filed: October 3, 2007
    Date of Patent: April 27, 2010
    Assignee: Konica Minolta Business Technologies, Inc.
    Inventors: Tomoya Ogawa, Tomohiro Suzuki, Yuji Tamura, Tetsuya Ishikawa, Hiroyasu Nishimura, Fumikage Uchida, Nao Moromizato, Munetoshi Eguchi, Kenji Okuyama
  • Patent number: 7692819
    Abstract: There is described an image processing apparatus which enables an additional image, such as a “Confidential” mark, to be added to an original image only during the period when it is necessary to be outputted. The image processing apparatus includes an image signals obtaining section which obtains image signals corresponding to an image; an additional image setting section which sets an additional image with the image corresponding to the image signals; a day and time information setting section which sets a day and time information used for judging whether the image is outputted with or without an additional image in outputting the image based on the image signals; and a judgment section which judges whether date and time information meets date and time for output when the image is outputted based on the image signals.
    Type: Grant
    Filed: May 24, 2005
    Date of Patent: April 6, 2010
    Assignee: Konica Minolta Business Technologies, Inc.
    Inventors: Masayuki Yasukaga, Tomohiro Suzuki, Yuji Tamura, Tetsuya Ishikawa, Hiroyasu Nishimura, Tomoya Ogawa, Fumikage Uchida, Nao Moromizato
  • Patent number: 7630586
    Abstract: An image processing apparatus comprises an input section which inputs a user identification information; and a registration section which registers an image data in association with the user identification information.
    Type: Grant
    Filed: October 21, 2005
    Date of Patent: December 8, 2009
    Assignee: Konica Minolta Business Technologies, Inc.
    Inventors: Masayuki Yasukaga, Tomohiro Suzuki, Yuji Tamura, Tetsuya Ishikawa, Hiroyasu Nishimura, Tomoya Ogawa, Fumikage Uchida, Nao Moromizato, Munetoshi Eguchi
  • Patent number: 7613895
    Abstract: A memory administrating method of administrating a memory divided into plural regions each of which consists of consecutive memory addresses, where the method includes the steps of: providing each region of the plural regions with usage information; and when releasing a release target region currently in use, determining usage of the release target region based on the usage information of at least one of neighboring regions positioned before and after the release target region.
    Type: Grant
    Filed: February 15, 2007
    Date of Patent: November 3, 2009
    Assignee: Konica Minolta Business Technologies, Inc.
    Inventors: Hiroyasu Nishimura, Tomohiro Suzuki, Yuji Tamura, Tetsuya Ishikawa, Tomoya Ogawa, Fumikage Uchida, Nao Moromizato, Masayuki Yasukaga, Munetoshi Eguchi
  • Patent number: 7508538
    Abstract: An image processing apparatus includes: a first memory for storing 2-D image data wherein pixels are arranged in a matrix in the main scanning direction and sub-scanning direction orthogonal to each other; a second memory; and a data control section for controlling the first memory and second memory, wherein at least one of the first and second memories is constituted by a SDRAM. The data control section reads the image data from the first memory in blocks of m pixels in the main scanning direction and n pixels in the sub-scanning direction (where n and m are natural numbers), writes the read data into the second memory, and transmits data to the memory composed of the SDRAM by burst transmission and continuous supply of desired column addresses, thereby allowing the read image data to be rotated.
    Type: Grant
    Filed: October 22, 2004
    Date of Patent: March 24, 2009
    Assignee: Konica Minolta Business Technologies, Inc.
    Inventors: Tomoya Ogawa, Tomohiro Suzuki, Yuji Tamura, Tetsuya Ishikawa, Hiroyasu Nishimura, Fumikage Uchida, Nao Moromizato, Masayuki Yasukaga
  • Publication number: 20080162822
    Abstract: A memory apparatus including: a cache control section to control a cache memory for an auxiliary storage apparatus; a volatile memory; and a nonvolatile memory, wherein the cache memory for the auxiliary storage apparatus is configured to have a volatile cache memory provided in the volatile memory and a nonvolatile cache memory provided in the nonvolatile memory, and wherein the cache control section accesses the nonvolatile cache memory using a write back method.
    Type: Application
    Filed: November 15, 2007
    Publication date: July 3, 2008
    Inventors: Kenji Okuyama, Tomohiro Suzuki, Yuji Tamura, Tetsuya Ishikawa, Hiroyasu Nishimura, Tomoya Ogawa, Fumikage Uchida, Nao Moromizato, Munetoshi Eguchi
  • Publication number: 20080086587
    Abstract: A data save apparatus including: a system memory, in which a plurality of segment regions having uneven capacities are provided; a nonvolatile memory, into which data having been memorized in the system memory are saved; and a controller which controls to save data with a unit of each of the segment regions into the nonvolatile memory from the system memory, wherein the controller determines whether saving data of each of the segment regions into the nonvolatile memory is necessary, and when a total capacity of segment regions, data in which having been determined to be necessary to be saved, reaches to a prescribed value, the controller transfers the data of the segment regions determined to be necessary to be saved into the nonvolatile memory by a DMA (Direct Memory Access) mode in descending order of segment region capacity.
    Type: Application
    Filed: October 5, 2007
    Publication date: April 10, 2008
    Inventors: Munetoshi EGUCHI, Tomohiro Suzuki, Yuji Tamura, Tetsuya Ishikawa, Hiroyasu Nishimura, Tomoya Ogawa, Fumikage Uchida, Nao Moromizato, Kenji Okuyama
  • Publication number: 20080086659
    Abstract: A data processing apparatus which saves data in a volatile memory into a nonvolatile memory when power is off, the data processing apparatus including: a detecting circuit for outputting: a momentary interruption detecting signal when a power source voltage is below a first threshold voltage, and a power failure detecting signal when the power source voltage is below a second threshold voltage that is lower than the first threshold voltage; and a control section adapted to start saving of the data in the volatile memory into the nonvolatile memory when the detecting circuit has output the momentary interruption detecting signal, continue save of the data, and carry out a predetermined shutdown processing when the detecting circuit has output the power failure detecting signal after the detecting circuit has output the momentary interruption detecting signal.
    Type: Application
    Filed: October 3, 2007
    Publication date: April 10, 2008
    Inventors: Tetsuya Ishikawa, Tomohiro Suzuki, Yuji Tamura, Hiroyasu Nishimura, Tomoya Ogawa, Fumikage Uchida, Nao Moromizato, Munetoshi Eguchi, Kenji Okuyama
  • Publication number: 20080086586
    Abstract: An information processing apparatus including: a nonvolatile memory; a volatile system memory in which predetermined data stored in the nonvolatile memory is developed; a control section to save the predetermined data stored in the system memory in the nonvolatile memory when a start of power-off operation is detected; and a storage section that stores a first timing information representing a time point of terminating the operation of saving the predetermined data in the nonvolatile memory, and a second timing information representing a power-off time point, wherein the control section compares the first timing information stored in the storage section with the second timing information, subsequent to the next operation of turning on of the power.
    Type: Application
    Filed: October 3, 2007
    Publication date: April 10, 2008
    Inventors: Tomoya Ogawa, Tomohiro Suzuki, Yuji Tamura, Tetsuya Ishikawa, Hiroyasu Nishimura, Fumikage Uchida, Nao Moromizato, Munetoshi Eguchi, Kenji Okuyama
  • Publication number: 20070271408
    Abstract: A memory administrating method of administrating a memory divided into plural regions each of which consists of consecutive memory addresses, comprising steps of: providing each region of the plural regions with usage information; and when releasing a release target region currently being in use, determining a usage of the release target region based on the usage information of at least one of neighboring regions positioned before and after the release target region.
    Type: Application
    Filed: February 15, 2007
    Publication date: November 22, 2007
    Inventors: Hiroyasu Nishimura, Tomohiro Suzuki, Yuji Tamura, Tetsuya Ishikawa, Tomoya Ogawa, Fumikage Uchida, Nao Moromizato, Masayuki Yasukaga, Munetoshi Eguchi
  • Publication number: 20070269138
    Abstract: An image processing apparatus comprises a memory; a store control section to divide and store image data in plural vacant memory regions in the memory; and an image administrating information registering section to register each divided image data divided by the store control section by correlating position information of each divided image data in the image data before dividing the image data with storing position information of each divided image data indicating a storing memory region.
    Type: Application
    Filed: March 7, 2007
    Publication date: November 22, 2007
    Inventors: Munetoshi Eguchi, Tomohiro Suzuki, Yuji Tamura, Tetsuya Ishikawa, Hiroyasu Nishimura, Tomoya Ogawa, Fumikage Uchida, Nao Moromizato, Masayuki Yasukaga
  • Publication number: 20070271419
    Abstract: A memory administrating method of administrating a memory divided into plural memory regions each of which consists of consecutive memory addresses, comprises steps of: acquiring a memory region from the plural memory regions; and registering at least one of usage information indicating the usage of the acquired memory region and time period information indicating the using time period for using the acquired memory region in an administrating portion of the acquired memory region.
    Type: Application
    Filed: February 15, 2007
    Publication date: November 22, 2007
    Inventors: Masayuki Yasukaga, Tomohiro Suzuki, Yuji Tamura, Tetsuya Ishikawa, Hiroyasu Nishimura, Tomoya Ogawa, Fumikage Uchida, Nao Moromizato, Munetoshi Eguchi
  • Publication number: 20070073911
    Abstract: To provide a system capable of avoiding an apparatus anomaly such as a system hang, even when an anomaly condition of connection in the cable connecting the apparatuses occurs. A first apparatus 10 in the transmission side includes: a data processing device 12; a buffer register 22 in which the processing device writes the data to be sent; a transmission section 23 for sending the data stored in the buffer register to a second apparatus 40 connected by a cable 3; and a loop detection section 27 for detecting an anomaly condition of connection in the cable during the data transmission. When detecting the anomaly condition of connection in the loop detection section, the first apparatus clears the buffer register to release the processing device from the data writing waiting, and at the same time the first apparatus notifies the processing device of the occurrence of the anomaly condition.
    Type: Application
    Filed: February 2, 2006
    Publication date: March 29, 2007
    Inventors: Munetoshi Eguchi, Tomohiro Suzuki, Yuji Tamura, Tetsuya Ishikawa, Hiroyasu Nishimura, Tomoya Ogawa, Fumikage Uchida, Nao Moromizato, Masayuki Yasukaga
  • Publication number: 20060282466
    Abstract: An image processing apparatus comprises an input section which inputs a user identification information; and a registration section which registers an image data in association with the user identification information.
    Type: Application
    Filed: October 21, 2005
    Publication date: December 14, 2006
    Applicant: Konica Minolta Business Technologies, Inc.
    Inventors: Masayuki Yasukaga, Tomohiro Suzuki, Yuji Tamura, Tetsuya Ishikawa, Hiroyasu Nishimura, Tomoya Ogawa, Fumikage Uchida, Nao Moromizato, Munetoshi Eguchi
  • Publication number: 20060126095
    Abstract: There is described an image processing apparatus which can add an additional image, such as a water mark, to an image to be processed and output those images. The image processing apparatus includes: an image signals obtaining section which obtains image signals corresponding to an image; a judgment section which judges whether date and time information meets date and time for output when the image is outputted based on the image signals; and an output section which outputs the image without an image relating to date and time information when the judgment section judges the date and time information meets the date and time for output, and outputs the image with the image relating to date and time information based on the date and time information when the judgment section judges the date and time information does not meet the date and time for output.
    Type: Application
    Filed: May 16, 2005
    Publication date: June 15, 2006
    Applicant: Konica Minolta Business Technologies, Inc.
    Inventors: Yuji Tamura, Tomohiro Suzuki, Tetsuya Ishikawa, Hiroyasu Nishimura, Tomoya Ogawa, Fumikage Uchida, Nao Moromizato, Masayuki Yasukaga
  • Publication number: 20060126096
    Abstract: There is described an image processing apparatus which enables an additional image, such as a “Confidential” mark, to be added to an original image only during the period when it is necessary to be outputted. The image processing apparatus includes an image signals obtaining section which obtains image signals corresponding to an image; an additional image setting section which sets an additional image with the image corresponding to the image signals; a day and time information setting section which sets a day and time information used for judging whether the image is outputted with or without an additional image in outputting the image based on the image signals; and a judgment section which judges whether date and time information meets date and time for output when the image is outputted based on the image signals.
    Type: Application
    Filed: May 24, 2005
    Publication date: June 15, 2006
    Inventors: Masayuki Yasukaga, Tomohiro Suzuki, Yuji Tamura, Tetsuya Ishikawa, Hiroyasu Nishimura, Tomoya Ogawa, Fumikage Uchida, Nao Moromizato
  • Publication number: 20060062473
    Abstract: An image reading apparatus comprises a reading section to read an original document having plural pages, and generate plural page data corresponding to the pages, a judging section to determine whether the page data includes at least one of a predetermined character, a predetermined symbol or predetermined attribution information, and an extracting section to extract a page which is determined to include at least one of the predetermined character, the predetermined symbol or the predetermined attribution information by the judging section.
    Type: Application
    Filed: April 18, 2005
    Publication date: March 23, 2006
    Applicant: Konica Minolta Business Technologies, Inc.
    Inventors: Nao Moromizato, Tomohiro Suzuki, Yuji Tamura, Tetsuya Ishikawa, Hiroyasu Nishimura, Tomoya Ogawa, Fumikage Uchida, Masayuki Yasukaga