Abstract: According to an embodiment, a semiconductor memory device comprises: a first wiring line; a memory string connected to this first wiring line; and a plurality of second wiring lines connected to this memory string. In addition, this memory string comprises: a first semiconductor layer connected to the first wiring line; a plurality of second semiconductor layers connected to this first semiconductor layer; and a variable resistance element connected between this second semiconductor layer and the second wiring line. Moreover, of the first semiconductor layer and the plurality of second semiconductor layers, one includes a semiconductor of a first conductivity type, and the other includes a semiconductor of a second conductivity type.

Abstract: According to an embodiment, a semiconductor memory device comprises: a first wiring line; a memory string connected to this first wiring line; and a plurality of second wiring lines connected to this memory string. In addition, this memory string comprises: a first semiconductor layer connected to the first wiring line; a plurality of second semiconductor layers connected to this first semiconductor layer; and a variable resistance element connected between this second semiconductor layer and the second wiring line. Moreover, of the first semiconductor layer and the plurality of second semiconductor layers, one includes a semiconductor of a first conductivity type, and the other includes a semiconductor of a second conductivity type.

Abstract: A semiconductor memory device according to an embodiment includes: a semiconductor substrate; and a memory cell array which is arranged above the semiconductor substrate in a first direction. The memory cell array includes: a semiconductor layer which extends in the first direction; a first conductive line which extends in a second direction crossing the first direction; a variable resistance film which is arranged at an intersection between the semiconductor layer and the first conductive line; a plurality of second conductive lines which are arranged in the second direction sandwiching the semiconductor layer and extend in the first direction; and a plurality of third conductive lines which are electrically connected to the second conductive lines. Two of the second conductive lines neighboring to each other in the second direction with the semiconductor layer interposed therebetween are electrically connected to different third conductive lines.

Abstract: According to an embodiment, a simulation method for resistance variations of a plurality of wires includes creating a numerical expression model for the resistance that is a function of parameters of a cross-sectional shape of the wire, based on the resistance calculated in a Monte Carlo Simulation, dividing each of the wires into a plurality of small elements in a length direction, calculating the resistance of each of the small elements by assigning the parameters of the cross-sectional shape characterizing the cross-sectional shape of each of the small elements to the numerical expression model, and calculating a sum of the resistances of the small elements in each of the wires.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell which stores data with two or more levels. The memory cell includes a structure includes a first electrode layer, a first semiconductor layer, a phase change film, an electrical insulating layer, a second semiconductor layer, and a second electrode layer arranged in order thereof, and the first semiconductor layer and the second semiconductor layer have carrier polarities different from each other.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device comprises memory cells each which stores data with two or more levels. Each of the memory cells includes a semiconductor layer, a first insulating layer on the semiconductor layer, a charge storage layer on the first insulating layer, a second insulating layer on the charge storage layer, and a control gate electrode on the second insulating layer, and the second insulating layer includes a ferroelectric layer.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device comprises memory cells each which stores data with two or more levels. Each of the memory cells includes a semiconductor layer, a first insulating layer on the semiconductor layer, a charge storage layer on the first insulating layer, a second insulating layer on the charge storage layer, and a control gate electrode on the second insulating layer, and the second insulating layer includes a ferroelectric layer.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell which stores data with two or more levels. The memory cell includes a structure includes a first electrode layer, a first semiconductor layer, a phase change film, an electrical insulating layer, a second semiconductor layer, and a second electrode layer arranged in order thereof, and the first semiconductor layer and the second semiconductor layer have carrier polarities different from each other.

Abstract: In one embodiment, a semiconductor device includes a substrate, and a plurality of interconnects provided in the same interconnect layer above the substrate. The device further includes a plurality of insulators provided so as to be buried between the plurality of interconnects. Moreover, the plurality of interconnects include an interconnect group in which 2N or more interconnects are successively arrayed so that correlation coefficients of line edge roughness (LER) between both side surfaces of the respective interconnects are positive, where N is an integer of 4 or more.

Abstract: In one embodiment, a semiconductor device includes a substrate, and a plurality of interconnects provided in the same interconnect layer above the substrate. The device further includes a plurality of insulators provided so as to be buried between the plurality of interconnects. Moreover, the plurality of interconnects include an interconnect group in which 2N or more interconnects are successively arrayed so that correlation coefficients of line edge roughness (LER) between both side surfaces of the respective interconnects are positive, where N is an integer of 4 or more.

Abstract: A transistor formed on a semiconductor substrate has a gate electrode formed via a gate insulating film and first and second diffusion layers formed in the semiconductor substrate, the first and second diffusion layers being positioned at both sides of the gate electrode. A first electrode is connected to the first diffusion layer of the transistor. A capacitor insulating film formed on the first electrode is formed of a silicon oxide film containing a substrate which is faster than Cu in diffusion velocity and which more readily reacts with oxygen than Cu does. A second electrode formed on the capacitor insulating film is formed of one of a Cu layer and another Cu layer containing the substance.

Abstract: A Monte Carlo simulation method for simulating movement of a carrier by alternately repeating a scattering process and a drift process, includes calculating, as a scattering time, a relaxation time by a Drude's formula in the scattering process, and determining a state of a carrier after the scattering, on the basis of a distribution function of a thermal equilibrium state.

Abstract: A nonvolatile semiconductor memory device includes: a semiconductor region; device isolation regions placed in the semiconductor region and extending in a column direction; a semiconductor layer placed on the semiconductor region and between the device isolation regions, and having a convex shape in cross section along a row direction; source/drain regions placed in the semiconductor layer and spaced from each other; a gate insulating film placed on the semiconductor layer between the source/drain regions; a floating gate electrode layer placed on the gate insulating film; an intergate insulating film placed on the floating gate electrode layer and upper surfaces of the device isolation regions; and a control gate electrode layer placed on the intergate insulating film and extending in the row direction.

Abstract: A semiconductor device simulation apparatus includes a first module configured to compute a reciprocal of the momentum relaxation time with respect to a part which is processed as an anisotropic scattering process of a carrier, and to compute the free-flight time by using the reciprocal of the momentum relaxation time, a second module configured to compute a drift process of the carrier during the free-flight time, and a third module configured to compute a scattering process by regarding a scattering a after of the drift process as an isotropic scattering, and by an output of the second module.

Abstract: A transistor formed on a semiconductor substrate has a gate electrode formed via a gate insulating film and first and second diffusion layers formed in the semiconductor substrate, the first and second diffusion layers being positioned at both sides of the gate electrode. A first electrode is connected to the first diffusion layer of the transistor. A capacitor insulating film formed on the first electrode is formed of a silicon oxide film containing a substrate which is faster than Cu in diffusion velocity and which more readily reacts with oxygen than Cu does. A second electrode formed on the capacitor insulating film is formed of one of a Cu layer and another Cu layer containing the substance.

Abstract: A transistor formed on a semiconductor substrate has a gate electrode formed via a gate insulating film and first and second diffusion layers formed in the semiconductor substrate, the first and second diffusion layers being positioned at both sides of the gate electrode. A first electrode is connected to the first diffusion layer of the transistor. A capacitor insulating film formed on the first electrode is formed of a silicon oxide film containing a substrate which is faster than Cu in diffusion velocity and which more readily reacts with oxygen than Cu does. A second electrode formed on the capacitor insulating film is formed of one of a Cu layer and another Cu layer containing the substance.

Abstract: A non-volatile semiconductor memory includes a plurality of memory cell transistors, each of the plurality of memory cell transistors includes: a source region having a first conductivity type and in contact with a buried insulating layer on a supporting substrate; a drain region having the first conductivity type and in contact with the buried insulating layer; and a channel region having the first conductivity type and provided between the source region and the drain region so as to contact the buried insulating layer, wherein a thickness of the channel region is more than one nm and not more than a value obtained by adding seven nm to a half value of a gate length of the memory cell transistor.

Abstract: A non-volatile semiconductor memory including a plurality of memory cell transistors, each of the plurality of memory cell transistors includes: a source region having a first conductivity type and in contact with a buried insulating layer on a supporting substrate; a drain region having the first conductivity type and in contact with the buried insulating layer; and a channel region having the first conductivity type and provided between the source region and the drain region so as to contact the buried insulating layer, wherein a thickness of the channel region is more than one nm and not more than a value obtained by adding seven nm to a half value of a gate length of the memory cell transistor.

Abstract: A semiconductor memory device includes: a semiconductor substrate; a semiconductor layer formed on the semiconductor substrate with an insulating film interposed therebetween, the semiconductor layer being in contact with the semiconductor substrate via an opening formed in the insulating film; and a NAND cell unit formed on the semiconductor layer with a plurality of electrically rewritable and non-volatile memory cells connected in series and first and second select gate transistors disposed at both ends thereof.

Abstract: A nonvolatile semiconductor memory device relating to one embodiment of this invention includes a substrate, a plurality of memory strings formed on said substrate, said memory string having a first select gate transistor, a plurality of memory cells and a second select gate transistor, said first select gate transistor having a first pillar semiconductor, a first gate insulation layer formed around said first pillar semiconductor and a first gate electrode being formed around said first gate insulation layer; said memory cell having a second pillar semiconductor, a first insulation layer formed around said second pillar semiconductor, a storage layer formed around said first insulation layer, a second insulation layer formed around said storage layer and first to nth electrodes (n is a natural number 2 or more) being formed around said second insulation layer, said first to nth electrodes being spread in two dimensions respectively, said second select gate transistor having a third pillar semiconductor, a se