Abstract: A chip-middle type fan-out panel-level package (FOPLP) has a routing layer, a polyimide layer formed on the routing layer and having a plurality of pillar openings and a chip opening, a plurality of metal pillars mounted on the routing layer through the corresponding pillar openings, a chip mounted on the first routing layer through the chip opening and a molding compound formed on the polyimide layer to encapsulate the metal pillars and the chip. The polyimide layer is used to control the warpage of the FOPLP. The polyimide layer is formed inside the FOPLP and the chip is directly mounted on the first routing layer through the chip opening, so a height of the FOPLP is not increased when the first PI layer is added.

Abstract: A semiconductor package including a die stack, an insulating encapsulation encapsulating the die stack, a first redistribution layer (RDL) and a second RDL disposed on two opposite sides of the insulating encapsulation, and a through insulating via disposed aside the die stack and extending through the insulating encapsulation to be electrically connected to the first RDL and the second RDL. The die stack includes a first die and a second die stacked upon one another and electrically connected to the first die. The second die includes a through semiconductor via disposed therein. One of the first die and the second die includes conductive features having different thicknesses. The second RDL is connected to the through semiconductor via of the second die. A manufacturing method of a semiconductor package is also provided.

Abstract: A method of forming a Fan-Out Wafer Level semiconductor device includes forming only a plurality of metal bonding pads on a glass carrier. Electrode pads of a semiconductor chip are coupled to the plurality of metal bonding pads. The semiconductor chip and the plurality of metal bonding pads are encapsulated with a molding compound. The glass carrier can then be removed to expose a surface of the FOWLP structure. A redistribution layer is then formed on the exposed surface of the FOWLP structure. At least one metal trace within the redistribution layer is in electrical contact with the plurality of metal bonding pads. Solder balls may be mounted on the redistribution layer to provide electrical contact between the solder balls and the electrode pads of the semiconductor chip.

Abstract: A semiconductor package including an insulating layer, a chip, a thermal interface material, a heat-dissipating cover and a re-distribution layer is provided. The insulating layer has an accommodating opening. The chip is disposed in the accommodating opening. The chip has an active surface, a back surface opposite to the active surface and a side surface connected to the active surface and the back surface. The thermal interface material is filled in the accommodating opening for at least encapsulating the side surface of the chip and exposing the active surface. The re-distribution layer and the heat-dissipating cover are disposed on two side of the insulating layer respectively. The heat-dissipating cover is thermally coupled to the chip through the thermal interface material. The re-distribution layer directly covers the insulating layer, the active surface of the chip and the thermal interface material, and the re-distribution layer is electrically connected to the chip.

Abstract: A semiconductor package including an insulating layer, a chip, a thermal interface material, a heat-dissipating cover and a re-distribution layer is provided. The insulating layer has an accommodating opening. The chip is disposed in the accommodating opening. The chip has an active surface, a back surface opposite to the active surface and a side surface connected to the active surface and the back surface. The thermal interface material is filled in the accommodating opening for at least encapsulating the side surface of the chip and exposing the active surface. The re-distribution layer and the heat-dissipating cover are disposed on two side of the insulating layer respectively. The heat-dissipating cover is thermally coupled to the chip through the thermal interface material. The re-distribution layer covers the active surface of the chip and the thermal interface material, and the re-distribution layer is electrically connected to the chip.

Abstract: A semiconductor package including an insulating layer, a chip, a thermal interface material, a heat-dissipating cover and a re-distribution layer is provided. The insulating layer has an accommodating opening. The chip is disposed in the accommodating opening. The chip has an active surface, a back surface opposite to the active surface and a side surface connected to the active surface and the back surface. The thermal interface material is filled in the accommodating opening for at least encapsulating the side surface of the chip and exposing the active surface. The re-distribution layer and the heat-dissipating cover are disposed on two side of the insulating layer respectively. The heat-dissipating cover is thermally coupled to the chip through the thermal interface material. The re-distribution layer covers the active surface of the chip and the thermal interface material, and the re-distribution layer is electrically connected to the chip.

Abstract: A semiconductor device includes a substrate, a stack of semiconductor chips, and a first sealing material. The substrate may include, but is not limited to, a chip mounting area and a higher-level portion. The higher level portion surrounds the chip mounting area. The higher-level portion is higher in level than the chip mounting area. The stack of semiconductor chips is disposed over the chip mounting area. A first sealing material seals the stack of semiconductor chips. The first sealing material is confined by the higher-level portion.

Abstract: A semiconductor device includes a wiring board, a stack of semiconductor chips, and a first sealing member. The wiring board has a first surface. The wiring board includes a first insulating layer formed over the first surface. The first insulating layer has a first opening. The stack of semiconductor chips is mounted over the first surface of the wiring board. The stack of semiconductor chips includes a first semiconductor chip. The first semiconductor chip is closer to the wiring board than the other semiconductor chips. The first sealing member seals at least the first semiconductor chip. The first sealing member includes a protruding portion. The first opening of the insulating layer faces toward the protruding portion of the first sealing member.

Abstract: A semiconductor device may include, but is not limited to a wiring board, a first insulator, a semiconductor chip, and a second insulator. The first insulator penetrates the wiring board. A top end of the first insulator is higher in level than an upper surface of the wiring board. The semiconductor chip is disposed on the top end of the first insulator. The semiconductor chip is separated from the upper surface of the wiring board. The second insulator covers the semiconductor chip and the upper surface of the wiring board.

Abstract: A semiconductor device includes a substrate, a stack of semiconductor chips, and a first sealing material. The substrate may include, but is not limited to, a chip mounting area and a higher-level portion. The higher level portion surrounds the chip mounting area. The higher-level portion is higher in level than the chip mounting area. The stack of semiconductor chips is disposed over the chip mounting area. A first sealing material seals the stack of semiconductor chips. The first sealing material is confined by the higher-level portion.

Abstract: A transparent conductive sheet comprises a silicon oxide gas barrier layer, an organosilicon compound-containing solvent-resistant layer and a transparent conductive layer laminated in that order on one side of a transparent plastic substrate, or a polyvinyl alcohol-based resin gas barrier layer and a solvent-resistant layer laminated in that order, over an anchor coat layer.