Abstract: A video signal processing apparatus comprises a component video signal demodulator to demodulate a component video signal sampled by a burst lock clock signal from a composite video signal sampled by the burst lock clock signal, the burst clock signal having multiplied frequency of a color subcarrier in the composite video signal having an auxiliary digital data signal inserted therein, and a re-sampling unit to convert sampling frequency of the component video signal selectively to a first frequency equal to or multiplied by horizontal synchronization frequency of the composite video signal or to a second frequency equal to or multiplied by frequency of the auxiliary digital data signal.

Abstract: A timing signal transferring circuit (10) that may be arranged to stably transfer a timing signal (S1) between two video signal processing circuits that may operate at different clock frequencies has been disclosed. A first timing signal (S1) may be received from a pre-stage video processing circuit (13). The first timing signal (S1) may be synchronous with a pre-stage system clock (C1) and may be set to the vicinity of a center of a screen by a video signal. A second timing signal (S2) may be generated on the basis of first timing signal (S1) and transferred to a post-stage video signal processing circuit (14). Second timing signal (S2) may be synchronous with a post-stage system clock (C2). In this way, a disturbance or distortion of a video on a screen due to a difference in system clock frequency affecting a video signal in the post-stage circuit may be reduced or eliminated.

Abstract: A timing signal transferring circuit (10) that may be arranged to stably transfer a timing signal (S1) between two video signal processing circuits that may operate at different clock frequencies has been disclosed. A first timing signal (S1) may be received from a pre-stage video processing circuit (13). The first timing signal (S1) may be synchronous with a pre-stage system clock (C1) and may be set to the vicinity of a center of a screen by a video signal. A second timing signal (S2) may be generated on the basis of first timing signal (S1) and transferred to a post-stage video signal processing circuit (14). Second timing signal (S2) may be synchronous with a post-stage system clock (C2). In this way, a disturbance or distortion of a video on a screen due to a difference in system clock frequency affecting a video signal in the post-stage circuit may be reduced or eliminated.

Abstract: A vertical drive circuit comprises a shift circuit composed of a plurality of cascaded half-bit scan circuits, a plurality of NAND gate circuits controlled by output signals of the scan circuits and control signals, and a plurality of output buffer circuits connected to the NAND gate circuits. A horizontal drive circuit comprises a shift circuit composed of a plurality of cascaded half-bit scan circuits, a plurality of first NAND gate circuits controlled by output signals of the scan circuits and control signals, a plurality of second NAND gate circuits controlled by output signals of the first NAND gate circuits and enable signals, and a plurality of data sampling and holding circuits controlled by output signals of the second NAND gate circuits.