Patents by Inventor Hiroyuki HIGASHIJIMA
Hiroyuki HIGASHIJIMA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230104638Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.Type: ApplicationFiled: December 5, 2022Publication date: April 6, 2023Inventors: Takahiro OCHIAI, Mitsuru GOTO, Hiroko SEHATA, Hiroyuki HIGASHIJIMA
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Patent number: 11532371Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.Type: GrantFiled: August 5, 2021Date of Patent: December 20, 2022Assignees: Japan Display Inc., Panasonic Liquid Crystal Display Co., Ltd.Inventors: Takahiro Ochiai, Mitsuru Goto, Hiroko Sehata, Hiroyuki Higashijima
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Publication number: 20210366564Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.Type: ApplicationFiled: August 5, 2021Publication date: November 25, 2021Inventors: Takahiro OCHIAI, Mitsuru GOTO, Hiroko SEHATA, Hiroyuki HIGASHIJIMA
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Patent number: 11114177Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.Type: GrantFiled: June 19, 2020Date of Patent: September 7, 2021Assignees: Japan Display Inc., Panasonic Liquid Crystal Display Co., Ltd.Inventors: Takahiro Ochiai, Mitsuru Goto, Hiroko Sehata, Hiroyuki Higashijima
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Publication number: 20200321068Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.Type: ApplicationFiled: June 19, 2020Publication date: October 8, 2020Inventors: Takahiro OCHIAI, Mitsuru GOTO, Hiroko SEHATA, Hiroyuki HIGASHIJIMA
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Patent number: 10726933Abstract: A plurality of cascade-connected register circuits which comprises a bidirectional shift register include a top register circuit, a bottom register circuit, and main register circuits. The register circuit has an output circuit which outputs one of four-phase clock pulses when a voltage of a first node is an active level; a second output circuit which outputs a non-active level when a voltage of a second node is the active level; a second node reset circuit which sets the second node to the non-active level when a voltage of a second node reset terminal is the active level. The forward scan signal sets the voltage of the first node of the top register circuit to the active level, and the forward scan signal sets the voltage of the second node reset terminal of the bottom register circuit to the active level.Type: GrantFiled: January 3, 2019Date of Patent: July 28, 2020Assignees: Japan Display Inc., Panasonic Liquid Crystal Display Co., Ltd.Inventors: Takahiro Ochiai, Mitsuru Goto, Hiroko Sehata, Hiroyuki Higashijima
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Publication number: 20190156905Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.Type: ApplicationFiled: January 3, 2019Publication date: May 23, 2019Inventors: Takahiro OCHIAI, Mitsuru GOTO, Hiroko SEHATA, Hiroyuki HIGASHIJIMA
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Patent number: 10210945Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.Type: GrantFiled: December 20, 2017Date of Patent: February 19, 2019Assignees: Japan Display Inc., Panasonic Liquid Crystal Display Co., Ltd.Inventors: Takahiro Ochiai, Mitsuru Goto, Hiroko Sehata, Hiroyuki Higashijima
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Publication number: 20180114584Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.Type: ApplicationFiled: December 20, 2017Publication date: April 26, 2018Inventors: Takahiro OCHIAI, Mitsuru GOTO, Hiroko SEHATA, Hiroyuki HIGASHIJIMA
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Patent number: 9881691Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.Type: GrantFiled: June 28, 2016Date of Patent: January 30, 2018Assignees: Japan Display Inc., Panasonic Liquid Crystal Display Co., Ltd.Inventors: Takahiro Ochiai, Mitsuru Goto, Hiroko Sehata, Hiroyuki Higashijima
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Patent number: 9793007Abstract: A bidirectional shift register capable of performing a stable shift operation in both directions and an image display device using the same are provided. In forward shift operation, when reference point N1 is at H level, (n+4)-th unit register circuit as a rear stage of the bidirectional shift register outputs pulse G(n+4) in synchronization with clock pulse V(n+4) inputted to (n+4)-th unit register circuit. A backward direction trigger signal VSTB is generated not only at the time of start of backward shift, but also, for example, in period (time t4 to t5) of one-phase clock immediately after G(n+4) is outputted in vertical blanking interval of the forward shift. The backward direction trigger signal VSTB is inputted to gate of a transistor provided to set reference point N1 of (n+4)-th unit register circuit to H level at the time of start of the backward shift.Type: GrantFiled: April 5, 2016Date of Patent: October 17, 2017Assignee: Japan Display Inc.Inventors: Takahiro Ochiai, Mitsuru Goto, Hiroyuki Higashijima, Yoshihiro Kotani, Shuuichirou Matsumoto
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Publication number: 20160307642Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.Type: ApplicationFiled: June 28, 2016Publication date: October 20, 2016Inventors: Takahiro OCHIAI, Mitsuru Goto, Hiroko Sehata, Hiroyuki Higashijima
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Patent number: 9406399Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.Type: GrantFiled: June 3, 2015Date of Patent: August 2, 2016Assignees: JAPAN DISPLAY INC., PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.Inventors: Takahiro Ochiai, Mitsuru Goto, Hiroko Sehata, Hiroyuki Higashijima
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Publication number: 20160217871Abstract: A bidirectional shift register capable of performing a stable shift operation in both directions and an image display device using the same are provided. In forward shift operation, when reference point N1 is at H level, (n+4)-th unit register circuit as a rear stage of the bidirectional shift register outputs pulse G(n+4) in synchronization with clock pulse V(n+4) inputted to (n+4)-th unit register circuit. A backward direction trigger signal VSTB is generated not only at the time of start of backward shift, but also, for example, in period (time t4 to t5) of one-phase clock immediately after G(n+4) is outputted in vertical blanking interval of the forward shift. The backward direction trigger signal VSTB is inputted to gate of a transistor provided to set reference point N1 of (n+4)-th unit register circuit to H level at the time of start of the backward shift.Type: ApplicationFiled: April 5, 2016Publication date: July 28, 2016Inventors: Takahiro OCHIAI, Mitsuru GOTO, Hiroyuki HIGASHIJIMA, Yoshihiro KOTANI, Shuuichirou MATSUMOTO
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Patent number: 9336899Abstract: A bidirectional shift register capable of performing a stable shift operation in both directions and an image display device using the same are provided. In forward shift operation, when reference point N1 is at H level, (n+4)-th unit register circuit as a rear stage of the bidirectional shift register outputs pulse G(n+4) in synchronization with clock pulse V (n+4) inputted to (n+4)-th unit register circuit. A backward direction trigger signal VSTB is generated not only at the time of start of backward shift, but also, for example, in period (time t4 to t5) of one-phase clock immediately after G(n+4) is outputted in vertical blanking interval of the forward shift. The backward direction trigger signal VSTB is inputted to gate of a transistor provided to set reference point N1 of (n+4)-th unit register circuit to H level at the time of start of the backward shift.Type: GrantFiled: December 22, 2011Date of Patent: May 10, 2016Assignee: Japan Display Inc.Inventors: Takahiro Ochiai, Mitsuru Goto, Hiroyuki Higashijima, Yoshihiro Kotani, Shuuichirou Matsumoto
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Publication number: 20150270012Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.Type: ApplicationFiled: June 3, 2015Publication date: September 24, 2015Inventors: Takahiro OCHIAI, Mitsuru GOTO, Hiroko SEHATA, Hiroyuki HIGASHIJIMA
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Patent number: 9076403Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.Type: GrantFiled: August 1, 2014Date of Patent: July 7, 2015Assignees: JAPAN DISPLAY INC., Panasonic Liquid Crystal Display Co., Ltd.Inventors: Takahiro Ochiai, Mitsuru Goto, Hiroko Sehata, Hiroyuki Higashijima
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Patent number: 8982033Abstract: A display device including various portions, circuits and other arrangements for outputting various pulses and triggers, for controlling forward shift and backward shift operations.Type: GrantFiled: August 1, 2014Date of Patent: March 17, 2015Assignees: Japan Display Inc., Panasonic Liquid Crystal Display Co., Ltd.Inventors: Takahiro Ochiai, Mitsuru Goto, Hiroko Sehata, Hiroyuki Higashijima
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Patent number: 8933870Abstract: In a unit drive circuit in each stage in a shift register, a transistor which is maintained in ON state during a period where the unit drive circuit in the stage does not perform an outputting operation is configured not to generate Vth shift. As switches, transistors T6A, T6B are connected between the output terminal OUT and AC power sources VA, VB. At least one of T6A, T6B is brought into ON state and T6A, T6B are alternately brought into OFF state during the period other than the outputting operation period. VA, VB supply L level during a period where T6A, T6B are in ON state, while VA, VB supply a ground potential GND which is an intermediate potential between an H level and an L level during a period where T6A, T6B are in OFF state.Type: GrantFiled: September 22, 2011Date of Patent: January 13, 2015Assignees: Japan Display Inc., Panasonic Liquid Crystal Display Co., Ltd.Inventors: Hiroyuki Higashijima, Takahiro Ochiai, Mitsuru Goto
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Patent number: 8912992Abstract: A display device includes a driving circuit that applies an active potential which is a potential for turning on pixel transistors sequentially to a plurality of output signal lines, wherein the driving circuit includes a main driving circuit that outputs the active potential to one end of the output signal line of the plurality of output signal lines by applying a clock signal caused by a input of the active potential output from the upper output signal line, and an auxiliary driving circuit that has an auxiliary transistor which is a transistor where the other end of the output signal line is connected to a signal line for the clock signal via the source or the drain. Thereby, output waveform distortion in the scanning signal line can be improved and thus display quality can be enhanced.Type: GrantFiled: April 2, 2012Date of Patent: December 16, 2014Assignee: Japan Display Inc.Inventors: Takahiro Ochiai, Mitsuru Goto, Hiroyuki Higashijima, Motoharu Miyamoto