Patents by Inventor Hiroyuki Iwata
Hiroyuki Iwata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220406514Abstract: A coil device includes a magnetic core, a first wire and a second wire, and a first terminal electrode and a second terminal electrode. The magnetic core includes a winding core portion and a flange portion. A first end of the first wire is connected to a first wire-joint portion of the first terminal electrode. A first end of the second wire is connected to a second wire-joint portion of the first terminal electrode. A second end of the first wire is connected to a first wire joint portion of the second terminal electrode. A second end of the second wire is connected to a second wire-joint portion of the second terminal electrode. The first wire-joint portion and the second wire-joint portion are arranged away from each other. The first wire-joint portion and the second wire joint portion are arranged away from each other.Type: ApplicationFiled: June 22, 2022Publication date: December 22, 2022Applicant: TDK CORPORATIONInventors: Hiroyuki IWATA, Kiyofumi FUJIWARA
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Publication number: 20210304943Abstract: The present invention provides a coil device which includes two coil elements in the same device and achieves an improved wire occupancy. The coil device includes a core including a winding core, and a winding wire part of which a first wire and a second wire are wound in a plurality of layers around the winding core, wherein the winding wire part includes a first part in which the first wire and the second wire of a same turn are wound adjacent to each other on a same layer, and a second part in which the first wire and the second wire of a same turn are wound in different layers without being adjacent to each other.Type: ApplicationFiled: March 23, 2021Publication date: September 30, 2021Applicants: TDK CORPORATION, TDK KOREA CORPORATIONInventors: Kiyofumi FUJIWARA, Hiroyuki IWATA, Eietsu ABE, Sepung KI, Chihu AN
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Publication number: 20210225580Abstract: A coil device including a magnetic core having a winding core around which a wire is wound to form a coil, and four terminal electrodes attached to an outer end surface of a flange formed at an end of the winding core along a winding axis. A recess is formed on the outer end surface of the flange, and each of the terminal electrodes includes a first rising piece loosely entering the recess, and a mounting piece integrally formed with the first rising piece and adhered to the outer end surface of the flange.Type: ApplicationFiled: January 8, 2021Publication date: July 22, 2021Applicants: TDK CORPORATION, TDK KOREA CORPORATIONInventors: Hiroyuki IWATA, Kiyofumi FUJIWARA, Sepung KI, Chihu AN
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Patent number: 10496771Abstract: In a compression scan, the number of test steps is reduced without reducing a defection efficiency. A semiconductor apparatus includes one or more scan chains each including one or more MMSFFs being serially connected and combinational circuits and can switch between a scan shift operation and a capture operation. The MMSFF includes an MUX that selects one of an external input test signal which is externally input and a shift test signal which is input via the MMSFF in a preceding stage in the same scan chain, and an FF that outputs one of the external input test signal and the shift test signal which has been selected by the MUX.Type: GrantFiled: December 9, 2015Date of Patent: December 3, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Hiroyuki Iwata
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Patent number: 10198542Abstract: In a compression scan, the number of test steps is reduced without reducing a defection efficiency. A semiconductor apparatus includes one or more scan chains each including one or more MMSFFs being serially connected and combinational circuits and can switch between a scan shift operation and a capture operation. The MMSFF includes an MUX that selects one of an external input test signal which is externally input and a shift test signal which is input via the MMSFF in a preceding stage in the same scan chain, and an FF that outputs one of the external input test signal and the shift test signal which has been selected by the MUX.Type: GrantFiled: December 9, 2015Date of Patent: February 5, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Hiroyuki Iwata
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Patent number: 10170234Abstract: A coil device includes a magnetic core and terminal electrodes. The terminal electrodes include attachment pieces, wire connection rising pieces, connection pieces, and fillet forming pieces. The wire connection rising pieces are integrally risen from one ends in a longitudinal direction of the attachment pieces along a side surface in the X-axis direction of a flange. The connection pieces are integrally formed with upper end sides of the wire connection rising pieces and have welded balls connected to lead parts of a wire by laser welding. The fillet forming pieces are integrally risen from one ends in a lateral direction crossing the longitudinal direction of the attachment pieces along a side surface in the Y-axis direction of the flange. Laser shielding members are arranged between the welded balls and the flange of a magnetic core.Type: GrantFiled: January 21, 2016Date of Patent: January 1, 2019Assignee: TDK CORPORATIONInventors: Hiroyuki Iwata, Nobuo Takagi, Hiroyuki Abe, Koji Shimura
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Patent number: 10078114Abstract: It is possible to reduce the number of test point circuits to be inserted necessary to accomplish a target fault coverage, to suppress an increase in an area overhead, and to reduce a test time. A test point circuit according to an embodiment constitutes a scan chain, and captures, in one capture operation period of a clock sequential test, a first operation result in a second capture clock that comes after a first capture clock, the first operation result having been captured by a test point circuit at a previous stage or a last stage of the scan chain in the first capture clock.Type: GrantFiled: July 27, 2016Date of Patent: September 18, 2018Assignee: Renesas Electronics CorporationInventors: Hiroyuki Iwata, Jun Matsushima
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Publication number: 20170089979Abstract: It is possible to reduce the number of test point circuits to be inserted necessary to accomplish a target fault coverage, to suppress an increase in an area overhead, and to reduce a test time. A test point circuit according to an embodiment constitutes a scan chain, and captures, in one capture operation period of a clock sequential test, a first operation result in a second capture clock that comes after a first capture clock, the first operation result having been captured by a test point circuit at a previous stage or a last stage of the scan chain in the first capture clock.Type: ApplicationFiled: July 27, 2016Publication date: March 30, 2017Inventors: Hiroyuki IWATA, Jun MATSUSHIMA
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Publication number: 20160274184Abstract: In a compression scan, the number of test steps is reduced without reducing a defection efficiency. A semiconductor apparatus includes one or more scan chains each including one or more MMSFFs being serially connected and combinational circuits and can switch between a scan shift operation and a capture operation. The MMSFF includes an MUX that selects one of an external input test signal which is externally input and a shift test signal which is input via the MMSFF in a preceding stage in the same scan chain, and an FF that outputs one of the external input test signal and the shift test signal which has been selected by the MUX.Type: ApplicationFiled: December 9, 2015Publication date: September 22, 2016Inventor: Hiroyuki IWATA
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Publication number: 20160217919Abstract: A coil device includes a magnetic core and terminal electrodes. The terminal electrodes include attachment pieces, wire connection rising pieces, connection pieces, and fillet forming pieces. The wire connection rising pieces are integrally risen from one ends in a longitudinal direction of the attachment pieces along a side surface in the X-axis direction of a flange. The connection pieces are integrally formed with upper end sides of the wire connection rising pieces and have welded balls connected to lead parts of a wire by laser welding. The fillet forming pieces are integrally risen from one ends in a lateral direction crossing the longitudinal direction of the attachment pieces along a side surface in the Y-axis direction of the flange. Laser shielding members are arranged between the welded balls and the flange of a magnetic core.Type: ApplicationFiled: January 21, 2016Publication date: July 28, 2016Inventors: Hiroyuki IWATA, Nobuo TAKAGI, Hiroyuki ABE, Koji SHIMURA
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Patent number: 8887015Abstract: An arithmetic processor executes analysis processing for analyzing a probability that an output value of the scan flip-flop circuit after the capturing operation becomes a given logical state, and scan chain structure processing for structuring a scan chain for a plurality of scan flip-flop circuits having the same degree of probability that the output value after the capturing operation becomes the given logical state, on the basis of a result of the analyzing processing. The scan chain lower in a transition probability during the scan operation is formed so that a power consumption during a scan test can be reduced.Type: GrantFiled: July 9, 2012Date of Patent: November 11, 2014Assignee: Renesas Electronics CorporationInventors: Hiroyuki Iwata, Jun Matsushima
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Publication number: 20130019134Abstract: An arithmetic processor executes analysis processing for analyzing a probability that an output value of the scan flip-flop circuit after the capturing operation becomes a given logical state, and scan chain structure processing for structuring a scan chain for a plurality of scan flip-flop circuits having the same degree of probability that the output value after the capturing operation becomes the given logical state, on the basis of a result of the analyzing processing. The scan chain lower in a transition probability during the scan operation is formed so that a power consumption during a scan test can be reduced.Type: ApplicationFiled: July 9, 2012Publication date: January 17, 2013Inventors: Hiroyuki IWATA, Jun MATSUSHIMA
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Publication number: 20040247326Abstract: An optical transmitter including a variable optical attenuator and a controller. The variable optical attenuator attenuates a light to be transmitted from the optical transmitter in accordance with a drive current of the attenuator. The attenuator has an attenuation versus drive current characteristic curve with a peak so that attenuation increases with increasing drive current on a side of the peak ascending to the peak and attenuation decreases with increasing drive current at an opposite side of the peak descending from the peak. The controller monitors the attenuated light and controls the drive current to maintain an attenuation amount near the peak. The attenuator is, for example, a Faraday rotator.Type: ApplicationFiled: May 19, 2004Publication date: December 9, 2004Applicant: Fujitsu LimitedInventors: Hiroyuki Iwata, Yoshio Nabeyama, Hiroshi Oikawa
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Publication number: 20040208569Abstract: Disclosed herein is a system having a first terminal device, a second terminal device, and an optical fiber transmission line for connecting the first and second terminal devices. The first terminal device includes a plurality of optical transmitters for respectively outputting a plurality of optical signals and an optical multiplexer for wavelength division multiplexing the optical signals output from the optical transmitters to obtain WDM signal light. The second terminal device includes an optical demultiplexer for separating the WDM signal light transmitted by the optical fiber transmission line into a plurality of optical signals and a plurality of optical receivers for respectively receiving the optical signals output from the optical demultiplexer.Type: ApplicationFiled: October 15, 2002Publication date: October 21, 2004Applicant: FUJITSU LIMITEDInventors: Yoshio Nabeyama, Hiroyuki Iwata
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Patent number: 6762837Abstract: In a polarization compensator for converting a polarization state of a lightwave, and a wavelength division multiplexing apparatus using same, a controller of the polarization compensator controls a rotator to orient a polarization plane of an input lightwave to a polarization plane of a reference polarizer. Also, the controller receives an output lightwave from the polarization compensator, of the above-mentioned present invention, which inputs the input lightwave through the rotator and a first ¼ wave plate, through a second ¼ wave plate and a polarizer having the polarization plane set in the reference direction, and the input lightwave is compensated to a linear polarization having the polarization plane of the reference direction based on a received polarization signal.Type: GrantFiled: October 23, 2001Date of Patent: July 13, 2004Assignee: Fujitsu LimitedInventor: Hiroyuki Iwata
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Patent number: 6721507Abstract: When a branching unit combines a first optical signal transmitted from a branch station with a second optical signal which is different in power level from the first optical signal and is transmitted from a terminal station A or B in an optical add-drop system, the S/N ratio of the lower power level of the two different power levels decreases, thereby deteriorating the system performance. Therefore, a dummy light is transmitted together with an optical signal to adjust the power level of the optical signal. Otherwise, an optical attenuator or an active optical signal level adjustment unit is provided for the branching unit so that both optical signals to be combined can be equal in level.Type: GrantFiled: April 30, 2002Date of Patent: April 13, 2004Assignee: Fujitsu LimitedInventors: Hiroyuki Iwata, Shinichirou Harasawa
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Publication number: 20020176080Abstract: In a polarization compensator for converting a polarization state of a lightwave, and a wavelength division multiplexing apparatus using same, a controller of the polarization compensator controls a rotator to orient a polarization plane of an input lightwave to a polarization plane of a reference polarizer. Also, the controller receives an output lightwave from the polarization compensator, of the above-mentioned present invention, which inputs the input lightwave through the rotator and a first ¼ wave plate, through a second ¼ wave plate and a polarizer having the polarization plane set in the reference direction, and the input lightwave is compensated to a linear polarization having the polarization plane of the reference direction based on a received polarization signal.Type: ApplicationFiled: October 23, 2001Publication date: November 28, 2002Applicant: FUJITSU LIMITEDInventor: Hiroyuki Iwata
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Publication number: 20020126353Abstract: When a branching unit combines a first optical signal transmitted from a branch station with a second optical signal which is different in power level from the first optical signal and is transmitted from a terminal station A or B in an optical add-drop system, the S/N ratio of the lower power level of the two different power levels decreases, thereby deteriorating the system performance. Therefore, a dummy light is transmitted together with an optical signal to adjust the power level of the optical signal. Otherwise, an optical attenuator or an active optical signal level adjustment unit is provided for the branching unit so that both optical signals to be combined can be equal in level.Type: ApplicationFiled: April 30, 2002Publication date: September 12, 2002Applicant: Fujitsu LimitedInventors: Hiroyuki Iwata, Shinichirou Harasawa
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Patent number: 6414770Abstract: When a branching unit combines a first optical signal transmitted from a branch station with a second optical signal which is different in power level from the first optical signal and is transmitted from a terminal station A or B in an optical add-drop system, the S/N ratio of the lower power level of the two different power levels decreases, thereby deteriorating the system performance. Therefore, a dummy light is transmitted together with an optical signal to adjust the power level of the optical signal. Otherwise, an optical attenuator or an active optical signal level adjustment unit is provided for the branching unit so that both optical signals to be combined can be equal in level.Type: GrantFiled: February 9, 2001Date of Patent: July 2, 2002Assignee: Fujitsu LimitedInventors: Hiroyuki Iwata, Shinichirou Harasawa
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Publication number: 20010015838Abstract: When a branching unit combines a first optical signal transmitted from a branch station with a second optical signal which is different in power level from the first optical signal and is transmitted from a terminal station A or B in an optical add-drop system, the S/N ratio of the lower power level of the two different power levels decreases, thereby deteriorating the system performance. Therefore, a dummy light is transmitted together with an optical signal to adjust the power level of the optical signal. Otherwise, an optical attenuator or an active optical signal level adjustment unit is provided for the branching unit so that both optical signals to be combined can be equal in level.Type: ApplicationFiled: February 9, 2001Publication date: August 23, 2001Inventors: Hiroyuki Iwata, Shinichirou Harasawa