Patents by Inventor Hiroyuki Kamijo

Hiroyuki Kamijo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060240176
    Abstract: A method for freeze drying confectionary is provided, whereby a confectionary is provided that can be stored for long periods of time without deformation. Further, a confectionery is provided using cream comprising 28 to 33 parts by weight of cream having a milk fat content of 42% to 48%, 28 to 33 parts by weight of cream having a milk fat content of 32% to 38%, 28 to 33 parts by weight of vegetable-based cream, and 5 to 10 parts by weight of sugar. The confectionery is freeze dried by: freezing the confectionery; subsequently setting the drying pressure to 0.60 to 0.65 Torr; performing primary sublimation by drying at a temperature of 25° C. to 40° C., for 3 to 4 hours; subsequently performing secondary sublimation by drying at a temperature of 60° C. to 70° C. for 18 to 20 hours; and further performing tertiary sublimation by drying at a temperature of 35° C. to 45° C. for 1.5 to 4.5 hours.
    Type: Application
    Filed: March 28, 2006
    Publication date: October 26, 2006
    Inventors: Keiichi Yamaguchi, Hironobu Tsujiguchi, Hiroyuki Kamijo, Shunzo Oike
  • Publication number: 20050133921
    Abstract: A semiconductor device comprises a semiconductor substrate, a multilayer interconnect provided on the semiconductor substrate, the multilayer interconnect comprising a plurality of layers of insulating films and interconnects, at least one fuse interconnect provided in a layer higher than the multilayer interconnect, and a moisture absorption preventing hollow member including a hollow structure, the moisture absorption preventing hollow member selectively surrounding the at least one fuse interconnect and reaching a surface of the semiconductor substrate through the multilayer interconnect, the moisture absorption preventing hollow member comprising a material having a lower hygroscopicity than the plurality of layers of insulating films.
    Type: Application
    Filed: October 28, 2004
    Publication date: June 23, 2005
    Inventors: Tomohiro Oki, Hiroyuki Kamijo
  • Patent number: 5238859
    Abstract: In the selective anisotropic etching by RIE of a first poly-Si film formed on a gate oxide film the poly-Si film is not entirely removed such that the poly-Si film is partly left unremoved. Then, the entire surface is covered with a second poly-Si film, followed by applying RIE. This particular technique permits preventing the gate oxide film near a poly-Si gate and the interface between the gate oxide film and the substrate from being damaged. Finally, a chemical dry etching, which does not do damage to the gate insulation film near the poly-Si gate, is applied to remove the second poly-Si film and the portion of the first polysilicon film thereunder.
    Type: Grant
    Filed: February 12, 1991
    Date of Patent: August 24, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Kamijo, Toshiro Usami, Yuuichi Mikata
  • Patent number: 5032535
    Abstract: In the selective etching by RIE, a poly-Si film formed on the gate oxide film is not entirely removed such that the poly-Si film is partly left unremoved. Then, the entire surface is covered with a poly-Si film, followed by applying RIE. The particular technique permits preventing the gate oxide film near a poly-Si gate and the interface between the gate oxide film and the substrate from being damaged. Finally, a chemical dry etching, which does not do damage to the gate insulation film near the poly-Si gate, is applied to remove the poly-Si film.
    Type: Grant
    Filed: April 21, 1989
    Date of Patent: July 16, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Kamijo, Toshiro Usami, Yuuichi Mikata
  • Patent number: 4958373
    Abstract: A defect-recognition processing apparatus converts into a defect image pattern, via a television camera, crystal defects present on the surface of an object under inspection, to process an image signal, by means of an image processing device, which corresponds to the defect image pattern, to measure rectangular images in terms of their length and their ratio between L.sub.Y and L.sub.X (L.sub.Y : a length in a longitudinal direction and L.sub.X : a length in the lateral direction of the wafer) and to detect defects developed on the surface of the aforementioned object.
    Type: Grant
    Filed: March 29, 1988
    Date of Patent: September 18, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiro Usami, Hiroyuki Kamijo, Takao Ohta, Masanobu Ogino
  • Patent number: 4931405
    Abstract: A method for manufacturing a semiconductor device is disclosed which selectively forms in a one-conductivity type semiconductor device a deep impurity-diffused area at over 1100.degree. C. in an H.sub.2 gas atmosphere containing N.sub.2, Ar, Ne, He and a combination thereof.
    Type: Grant
    Filed: February 6, 1989
    Date of Patent: June 5, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Kamijo, Yuuichi Mikata