Patents by Inventor Hiroyuki Kamijou

Hiroyuki Kamijou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6919260
    Abstract: A semiconductor substrate having a shallow trench isolation (STI) structure and a method of manufacturing the same are provided, i.e., an isolation substrate in which grooves are selectively formed at predetermined locations of the semiconductor substrate and oxide films using organic silicon source as material are buried in the grooves as buried oxide films. The present invention is characterized in that the buried oxide films are annealed at a predetermined temperature within the range of 1100 to 1350° C. before or after planarization of the semiconductor substrate such that ring structures of more than 5-fold ring and ring structures of less than 4-fold ring are formed at predetermined rates in the buried oxide films. The above annealing allows stress of the oxide film buried in the grooves to be relaxed. Hence, the generation of dislocation is suppressed.
    Type: Grant
    Filed: July 21, 1999
    Date of Patent: July 19, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kaori Umezawa, Norihiko Tsuchiya, Yoshiaki Matsushita, Hiroyuki Kamijou, Atsushi Yagishita, Tsunehiro Kita
  • Patent number: 5994756
    Abstract: A semiconductor substrate having a shallow trench isolation (STI) structure and a method of manufacturing the same are provided, i.e., an isolation substrate in which grooves are selectively formed at predetermined locations of the semiconductor substrate and oxide films using organic silicon source as material are buried in the grooves as buried oxide films. The present invention is characterized in that the buried oxide films are annealed at a predetermined temperature within the range of 1100 to 1350.degree. C. before or after planarization of the semiconductor substrate such that ring structures of more than 5-fold ring and ring structures of less than 4-fold ring are formed at predetermined rates in the buried oxide films. The above annealing allows stress of the oxide film buried in the grooves to be relaxed. Hence, the generation of dislocation is suppressed.
    Type: Grant
    Filed: November 20, 1996
    Date of Patent: November 30, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kaori Umezawa, Norihiko Tsuchiya, Yoshiaki Matsushita, Hiroyuki Kamijou, Atsushi Yagishita, Tsunehiro Kita
  • Patent number: 5854133
    Abstract: According to the present invention, to flatten the surface of a silicon substrate by polishing an element isolating buried insulation film by chemical mechanical polishing, a polysilicon film is formed on the top surface of a projection of a silicon substrate. After that, a buried insulation film is formed all over the silicon substrate along the irregularities thereof. A carbon film is formed on the surface of a recess of the buried insulation film. Using the carbon film as a stopper, the buried insulation film is polished by the chemical mechanical polishing to ease the irregularities of the surface of the polished insulation film. Then the carbon film is removed and, using the polysilicon film as a stopper, the buried insulation film is polished by the chemical mechanical polishing to flatten the surface of the polished insulation film. Thus, the flatness of the buried insulation film can easily be controlled, and the surface of the silicon substrate can always be flattened satisfactorily.
    Type: Grant
    Filed: August 15, 1996
    Date of Patent: December 29, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takayo Hachiya, Moto Yabuki, Hiroyuki Kamijou