Abstract: A data processing system incorporating a main memory for storing instructions and operands and performing data processing in a mode of microprogram control system in response to instructions read out of the main memory. The system translates an instruction word read out of the main memory into an intermediate machine word having the orthogonal format, and addresses a microprogram memory in correspondence to the instruction word by analyzing the intermediate machine word. The system further incorporates a plurality of register sets so that each different task can use an individual register set, and a memory for memorizing the number of registers holding parameters used commonly among procedures corresponding to the register sets, so that the number of registers for each use can be changed arbitrarily for each register set by using the memory.

Abstract: A variable wave forming circuit is provided which produces signals of various waveforms (e.g., sine, triangular or trapezoidal waves) and various frequencies. A random access memory (memory means) 121 to store wave formation information on waveform is provided. According to the wave formation information stored in the memory means, the updating or keeping of a digital value in an increment/decrement circuit 123 is controlled and the digital value is digital/analog-converted by a digital/analog (D/A) conversion circuit 124, which is controlled by a digital value control means that includes the increment/decrement circuit 123. By writing appropriate wave formation information into the memory means, it is possible to produce signals of desired waveforms.

Abstract: A bus error ascribable to a bus master module other than a central processing unit (CPU) is set as a specified factor for an exception process. When the exception process is requested, the CPU carries a corresponding service program for the exception process into execution without executing a process for altering and setting mask bits as is executed for an interrupt request. Thus, the exception process request specific to the bus error is not undesirably refused by the interrupt request etc. accepted before the bus error, and besides, a period of time which is expended before the start of the run of a service program corresponding to the bus error is shortened, with the result that the reliability of the process for the bus error attributed to the predetermined bus master module other than the CPU is enhanced.

Abstract: A multiplication, division and square root extraction apparatus which calculates the solutions to addition, division and square root extraction functions by approximation using iteration has a multiplier, an adder-subtracter and a shifter of prescribed bit width connected to a bus. Iteration is conducted by inputting the output of the multiplier to the adder-subtracter or the shifter and returning the result to the input of the multiplier via the bus. A shifter and an arithmetic and logic unit connected to a second bus connected to the aforesaid bus via a switch have a greater bit width than the prescribed bit width and are used for large scale calculations, thus preventing a reduction in processing speed.

Abstract: A circuit by which an SWI instruction held in a memory circuit is switchedly input in response to a signal supplied externally is provided in a processor, whereby the substitution of a program word can be realized using such an internal circuit, so that a high-speed and reliable break in program excution can be effected. Moreover, an interrupt function separate from normal interrupts is established by setting a specified operation mode, whereby, when a data processor is used as an emulator, the break of a user program including the ordinary interrupt processes can be easily effected by utilizing the special interrupt function. Also, by additionally providing the function of delivering out a signal indicative of the break status, an external circuit can be simplified.

Abstract: A method and apparatus for controlling a plurality of bus interfaces in a system including on one chip a central processing unit and an internal memory. A first operand retrieving operation is executed by a first operand retrieving unit when one operand is discriminated that is located outside a chip, and a second operand retrieving operation is executed by a second operand retrieving unit when another operand is discriminated that is located inside the chip, so that the operand is read to the central processing unit in accordance with the bus interface signals of the first and the second operand retrieving units.

Abstract: Micro instructions having a predetermined relationship with respect to each other are modified so that an original micro instruction and address assigned thereto can be restored by combining one or more modified micro instructions and address assigned thereto. A microprogram memory stores the micro instructions in such a modified form and at the modified address. When an original address is designated, one or more term lines are activated in a decoder of the microprogram memory, and modified micro instructions corresponding to the activated term lines are read-out from a memory array of the microprogram memory. The read modified micro instructions are logically combined to restore the original micro instruction. Thereby, the number of micro instructions to be actually stored in the microprogram memory can be reduced.

Abstract: On a single semiconductor chip, there are provided an arithmetic logic unit, a general-purpose register for storing data to be processed and data as a result of the operation in the arithmetic logic unit, a peripheral register used for performing the peripheral functions required, a buffer register and an internal bus line through which the above mentioned components conduct the data communication with one another. Further, there is provided on the chip a microprogram storage and control device which stores microinstructions for processing instructions read out from a main memory (an instruction processing) and data processing necessary for performing the required peripheral functions (an auxiliary function processing).