Abstract: A gate electrode has a relatively long gate length of e.g., about 10 &mgr;m. In a region immediately above the gate electrode which is sandwiched between first-layer metals provided is a metal dummy pattern having a width in the first direction and extending in the second direction perpendicular to a direction of gate length (direction of current flow). Moreover, a geometric center of the metal dummy pattern in the second direction is equal to a geometric center of the gate electrode in the second direction. This maintains the symmetry in shape of the metal dummy pattern as viewed from the gate electrode. Such a structure can make deterioration in characteristics of a plurality of elements uniform while maintaining the essential effect of a metal CMP.

Abstract: A gate electrode (1) has a relatively long gate length (L) of e.g., about 10 &mgr;m. In a region immediately above the gate electrode (1) which is sandwiched between first-layer metals (1AL; 4, 5) provided is a metal dummy pattern (6) having a width (W:<L) in the first direction (D1) and extending in the second direction (D2) perpendicular to a direction of gate length (direction of current flow). Moreover, a geometric center of the metal dummy pattern (6) in the second direction (D2) is equal to a geometric center (GC) of the gate electrode (1) in the second direction (D2). This maintains the symmetry in shape of the metal dummy pattern (6) as viewed from the gate electrode (1). Such a structure can make deterioration in characteristics of a plurality of elements uniform while maintaining the essential effect of a metal CMP.

Abstract: A gate electrode has a relatively long gate length of e.g., about 10 &mgr;m. In a region immediately above the gate electrode which is sandwiched between first-layer metals provided is a metal dummy pattern having a width in the first direction and extending in the second direction perpendicular to a direction of gate length (direction of current flow). Moreover, a geometric center of the metal dummy pattern in the second direction is equal to a geometric center of the gate electrode in the second direction. This maintains the symmetry in shape of the metal dummy pattern as viewed from the gate electrode. Such a structure can make deterioration in characteristics of a plurality of elements uniform while maintaining the essential effect of a metal CMP.

Abstract: A gate electrode (1) has a relatively long gate length (L) of e.g., about 10 &mgr;m. In a region immediately above the gate electrode (1) which is sandwiched between first-layer metals (1AL; 4, 5) provided is a metal dummy pattern (6) having a width (W:<L) in the first direction (D1) and extending in the second direction (D2) perpendicular to a direction of gate length (direction of current flow). Moreover, a geometric center of the metal dummy pattern (6) in the second direction (D2) is equal to a geometric center (GC) of the gate electrode (1) in the second direction (D2). This maintains the symmetry in shape of the metal dummy pattern (6) as viewed from the gate electrode (1). Such a structure can make deterioration in characteristics of a plurality of elements uniform while maintaining the essential effect of a metal CMP.

Abstract: A digital-analog converter has unit current source cells each having a differential switch circuit and a constant current source. The differential switch circuit made of two switches is driven by a pair of complementary driving circuits controlled by a bit signal and the inverted bit signal corresponding to that signal and entered simultaneously. The constant current source outputs a constant current to a first and a second current output terminal via the switch circuit. The signals for controlling the driving circuits that drive the switches are such that the delay time for the switch closing operation will be longer than the delay time for the switch opening operation. As a result, the cross point of the two signals to open and close the switches in a complementary manner becomes greater than the median between the maximum and minimum signal levels.

Abstract: An output buffer circuit operating normally when its supply potential is exceeded by the potential of the bus to which the buffer circuit output is connected. The circuit comprises a p-channel MOS transistor and a first and a second n-channel MOS transistor. The output node of the output buffer circuit is connected not to the p-channel MOS transistor but to the connection point between the source of the first n-channel MOS transistor and the drain of the second n-channel MOS transistor. The threshold potential of the first n-channel MOS transistor is set so that, with the output node in the high-impedance state, the first n-channel MOS transistor is turned off when the output node potential exceeds the supply potential of the output buffer circuit. This prevents the p-channel MOS transistor from getting activated or from being forward-biased between the back gate and the drain or source. Thus no leak current flows when the bus potential becomes higher than the supply potential of the output buffer circuit.

Abstract: An upper comparator group compares an analog signal with upper reference potentials applied from upper ladder resistance network. A switch group outputs the predetermined intermediate reference potential of the ladder resistance network to an analog subtracting circuit in response to the upper comparison results. The analog subtracting circuit subtracts the intermediate reference potential from the analog signal for producing an input signal for use in the lower side. A lower ladder resistance network outputs lower reference potentials obtained by dividing by resistors constant static intermediate reference potentials of the ladder resistance network applied from a differential amplifying circuit. A lower comparator group compares the lower reference potentials with the input signal for lower comparison. The upper and the lower comparison results are converted into a digital signal by upper and the lower encoders and the adding/subtracting circuit.

Abstract: In order to obtain a constant current circuit which has an excellent constant current property and requires no plural bias circuits, a base of an NPN bipolar transistor (5) and a gate of an N-channel MOS transistor (6) are connected to a first terminal (1) in common. A collector of the transistor (5) is connected to a second terminal (2) and a source of a transistor (6) is connected to a third terminal respectively, while a voltage source (59) is connected between the first and third terminals. An emitter of the transistor (5) is connected with a drain of the transistor (6). Identical bias voltages are supplied to the base and the gate, while a gate-to-drain voltage of the transistor (6) is equal to a base-to-emitter voltage of the transistor (5). Thus, the transistor (6) operates in a pentode region, to serve as a constant current load for the transistor (5).

Abstract: The present invention is directed to improvement of a differential amplifier an its peripheral components employed in an A/D converter to enhance an accuracy of the A/D converter. The differential amplifier has an amplifying element comprised of a pair of differential transistors Q1 and Q2, emitter resistances 2a and 2b, and collector resistances 2c and 2d. The differential amplifier has transistors Q3 and Q4 constituting an emitter follower for applying an output amplified in the differential amplifying element to the outside. The differential amplifier includes transistors Q5 and Q6 having their respective base electrodes connected to input terminals 4a and 4b and serially connected to the transistors Q3 and Q4, and resistances 2e and 2f interposed between emitter electrodes of the transistors Q5 and Q6 so as to relieve any influence of variations in base-emitter voltages of the transistors Q3 and Q4.

Abstract: An A/D converter main body is formed in the form of an annulus with a wiring region set as its center, and a ladder resistor array for dividing an input reference voltage and an analog signal line for applying an input analog signal to each comparator in the A/D converter are formed in the form of an annulus with the wiring region set as a center. Wirings from terminals are once concentrated into the wiring region by an input/output line group and then distributed therefrom to circuit elements. Since the ladder resistor array is formed in a circular form, resistance values are less liable to change as compared to the case where the ladder resistor array is bent, resulting in a higher precision of reference voltages for comparison. Further, wiring lengths for control signals to be applied to the circuit elements are made equal, and there is no fear of line delays in the control signals.

Abstract: An improved differential subtracter 3a and an improved D/A converter 7a are used in a two-step parallel A/D converter 100. The D/A converter is responsive to complementary signals S1-S2 and B1-Bn indicative of results of conversion of higher bits to draw subtraction currents Is1 and Is2 through emitter electrodes of npn transistors Q1 and Q2. Since a difference between emitter currents I.sub.E1 and I.sub.E2 is small, base-emitter voltages V.sub.BE1 and V.sub.BE2 are substantially equal to each other. As a result, the A/D converter can execute the subtraction at high speed with high accuracy.

Abstract: A binary data converter is adapted to convert a positive binary data into a negative binary data represented by a complement on two and vice verse. The conversion is effected as follows. A least significant bit of an inputted binary data is outputted as the least significant bit of the converted binary date as it is. With respect to bit signal other than the least significant bit, respective input bit signals less significant than the corresponding input bit signal are ORed. Depending on the result thereof, inverted or non-inverted signals of the corresponding input bit signals are outputted as the bit signals of the converted binary data. Therefore, carry delay is not generated, and thus the operation speed can be increased. Further, the simple circuit structures can reduce the number of required elements.

Abstract: A semiconductor integrated circuit device having semiconductor integrated circuit blocks disposed close to each other. An insulating layer is interposed between each adjacent pair of the semiconductor integrated circuit blocks. An electroconductive shield member is formed between the adjacent semiconductor integrated circuit blocks to limit the capacitive coupling therebetween. The shield member is electrically insulated from the semiconductor integrated circuit blocks and is maintained at a predetermined fixed potential.

Abstract: The inventive multilayer semiconductor integrated circuit has a columnar semiconductor region provided between adjacent two layers and a control electrode provided in the vicinity of the columnar semiconductor region. The transference of a signal between the adjacent two layers is carried out through the columnar semiconductor region the electric conductivity of which is controlled by a control signal applied to the control electrode. That is, the area corresponding to the columnar semiconductor region functions as an active element.

Abstract: A multiplication processing circuit requiring no digital-analog converter includes a circuit for multiplying a digital multiplication coefficient by a digital multiplicand and outputting the result of multiplication as an analog current signal. The multiplication processing circuit includes a circuit for decoding the digital multiplication coefficient to generate one or a plurality of control signals, a circuit responsive to the digital multiplicand and to the generated control signal for generating a signal indicating, in decimal notation, the result of multiplication of the digital multiplication coefficient by the digital multiplicand, and a circuit for converting the signal indicating the result of multiplication into an analog current signal of a corresponding magnitude. Each of the control signals indicates at least one digital multiplication coefficient in decimal notation.