Abstract: A lateral bipolar transistor capable of forming a narrow-sized diffusion region, such as a base width, is disclosed. The transistor exhibits no scattering in the direction of the depth of the width of the diffusion region. Emitter resistance is reduced by varying an impurity diffusion source at substantially a uniform concentration in a semiconductor portion and forming a diffusion region by diffusion from the impurity diffusion source. The bipolar transistor has an SOI structure. A method of making such device is also disclosed.

Abstract: A lateral bipolar transistor capable of forming a narrow-sized diffusion region, such as a base width, is disclosed. The transistor exhibits no scattering in the direction of the depth of the width of the diffusion region. Emitter resistance is reduced by varying an impurity diffusion source at substantially a uniform concentration in a semiconductor portion and forming a diffusion region by diffusion from the impurity diffusion source. The bipolar transistor has an SOI structure. A method of making such device is also disclosed.

Abstract: A process and an apparatus for forming a gasket directly on a workpiece having a joining surface which has an annular gasket-fixing groove, wherein a mold having a gasket-forming groove which cooperates with the gasket-fixing groove to define a cavity for forming the gasket is clamped to the joining surface of the workpiece, and a material is injected into the cavity through an injection passage which is formed through the mold and which communicates with the gasket-forming groove. The material is cured into the gasket, and the mold is removed from the workpiece. The mold may have two elastic sealing members disposed on inner and outer sides of the gasket-forming groove, respectively, so as to extend along the gasket-forming groove, and provide pressure-tight sealing of the cavity when the body is placed on the workpiece such that the sealing members are held in elastic pressure-tight contact with the joining surface.

Abstract: In production of a Bi-CMOS semiconductor device, when forming a lateral PNP transistor in a bipolar section, an oxide film is deposited on this base area to prevent etching damages such as those in forming an LDD spacer for a MOS section, thus degradation of the lateral PNP bipolar transistor and drop of yield in production thereof being prevented and a high performance (low cost) Bi-CMOS LSI being realized.

Abstract: A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor device is manufactured by the method including the steps of forming a first impurity diffused layer of a first conduction type in a semiconductor substrate; forming a conducting film connected to the first impurity diffused layer; forming a first insulating film on the conducting film; forming a first hole through a laminated film composed of the first insulating film and the conducting film; forming a second impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the first hole; forming a side wall from a second insulating film in the first hole to form a second hole; and forming a third impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the second hole.

Abstract: A method for producing a semiconductor device which decrease the number of processes at the time of producing BiCMOSLSI than the usual. Impurities are introduced into a semiconductor substrate under a second insulating film and a first electric conductive film utilizing a first insulating film and the first conductive film formed on the semiconductor substrate as masks. Therefore, it is able to perform concurrent introduction of impurities into the gate electrode, the source and the drain of the MOSFET, the base electrode of the bipolar transistor, the emitter and the collector contact of the lateral bipolar transistor, the outlet electrode of the capacitor, and the resistor, so that the number of process steps can be reduced.

Abstract: A hole in the site for the emitter layer of the npn transistor of a complementary bipolar transistor is made in a step independent from a step of making a hole in the site for the emitter layer of the pnp transistor, and an n.sup.+ -type polycrystalline Si film doped with an n-type impurity upon being made is used to make the emitter electrode of the npn transistor. Independently from this step, a p.sup.+ -type polycrystalline Si film doped with a p-type impurity upon being made is used to make the emitter electrode of the pnp transistor. The n-type impurity diffusing from the emitter electrode makes an n.sup.+ -type emitter layer of the npn transistor, whereas the p-type impurity diffusing from the emitter electrode makes a p.sup.+ -type emitter layer of the pnp transistor. Thus the method can produce complementary bipolar transistors with a higher performance, and is suitable for combination with a process for fabricating sub-half-micron bipolar CMOSs.

Abstract: A lateral bipolar transistor capable of forming a narrow-sized diffusion region, such as a base width, is disclosed. The transistor exhibits no scattering in the direction of the depth of the width of the diffusion region. Emitter resistance is reduced by varying an impurity diffusion source at substantially a uniform concentration in a semiconductor portion and forming a diffusion region by diffusion from the impurity diffusion source. The bipolar transistor has an SOI structure. A method of making such device is also disclosed.

Abstract: A semiconductor device comprising a MIS structure comprising a first electrically conductive film formed on an oxide film, a second electrically conductive film formed on at least a part of said first electrically conductive film, an insulator film formed on said second electrically conductive film, and a third electrically conductive film formed on said insulator film; and at least one electrode contact portion formed on said first electrically conductive film. A semiconductor device comprising a MIS capacitor having a diffusion layer inside the semiconductor substrate as a lower electrode with a first electrically conductive type being isolated using another diffusion layer having the opposite conductive type, and said another diffusion layer having the opposite conductive type being further isolated using a diffusion layer for isolation having the first conductive type and which is earthed.

Abstract: A method of making a semiconductor device wherein fluctuations of an effective length of the conduction area and placement thereof relative to source and drain regions is controlled during manufacture. A first insulation film is formed on a semiconductor substrate. A first thin film is formed on the first insulation film. A trench is formed below a surface of the substrate by etching said first thin film, first insulation film, and semiconductor substrate. A second insulation film is formed along an inside wall of the trench. A first electrically conductive film is formed along an inside wall of the second insulation film within the trench and an embedded electrode is formed within a space defined by said first electrically conductive film.

Abstract: A lateral bipolar transistor capable of forming a narrow-sized diffusion region, such as a base width, is disclosed. The transistor exhibits no scattering in the direction of the depth of the width of the diffusion region. Emitter resistance is reduced by varying an impurity diffusion source at substantially a uniform concentration in a semiconductor portion and forming a diffusion region by diffusion from the impurity diffusion source. The bipolar transistor has an SOI structure. A method of making such device is also disclosed.

Abstract: A lateral bipolar transistor capable of forming a narrow-sized diffusion region, such as a base width, is disclosed. The transistor exhibits no scattering in the direction of the depth of the width of the diffusion region. Emitter resistance is reduced by varying an impurity diffusion source at substantially a uniform concentration in a semiconductor portion and forming a diffusion region by diffusion from the impurity diffusion source. The bipolar transistor has an SOI structure. A method of making such device is also disclosed.

Abstract: A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor device is manufactured by the method including the steps of forming a first impurity diffused layer of a first conduction type in a semiconductor substrate; forming a conducting film connected to the first impurity diffused layer; forming a first insulating film on the conducting film; forming a first hole through a laminated film composed of the first insulating film and the conducting film; forming a second impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the first hole; forming a side wall from a second insulating film in the first hole to form a second hole; and forming a third impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the second hole.

Abstract: In production of a Bi-CMOS semiconductor device, when forming a lateral PNP transistor in a bipolar section, an oxide film is deposited on this base area to prevent etching damages such as those in forming an LDD spacer for a MOS section, thus degradation of the lateral PNP bipolar transistor and drop of yield in production thereof being prevented and a high performance (low cost) Bi-CMOS LSI being realized.

Abstract: A semiconductor device comprising a MIS structure comprising a first electrically conductive film formed on an oxide film, a second electrically conductive film formed on at least a part of said first electrically conductive film, an insulator film formed on said second electrically conductive film, and a third electrically conductive film formed on said insulator film; and at least one electrode contact portion formed on said first electrically conductive film. A semiconductor device comprising a MIS capacitor having a diffusion layer inside the semiconductor substrate as a lower electrode with a first electrically conductive type being isolated using another diffusion layer having the opposite conductive type, and said another diffusion layer having the opposite conductive type being further isolated using a diffusion layer for isolation having the first conductive type and which is earthed.

Abstract: According to this invention, a base extracting electrode is formed using a polysilicon side wall self-aligned with a base region so as to reduce a collector-base parasitic capacitance of a transistor. A base layer is formed on a semiconductor substrate by a selective epitaxial method using an MBE method to obtain a high-speed operation. A high impurity-concentration region is formed on a buried layer immediately below an emitter by pedestal ion implantation to reduce a collector series resistance. In addition, a specific layer of a plurality of polysilicon layers is selectively annealed by radiation of an eximer laser to operate the transistor at high speed and to obtain a highly accurate resistor element.

Abstract: A method of manufacturing a semiconductor device having a bipolar transistor and a MOS transistor is disclosed, which comprises covering the bipolar transistor formation region with a gate insulating film and also with a first gate formation material at the time of the MOS transistor gate formation, removing the first gate formation material and gate insulating film covering at least a portion of the bipolar transistor formation region, thus forming an opening in the gate insulating film and first gate formation material, forming a second gate formation material, removing other portion of the first and second gate formation materials than on the bipolar transistor formation region and the MOS transistor gate formation region, forming an inter-layer insulating film, and removing the inter-layer insulating film and first and second gate formation materials on at least a portion of the bipolar transistor formation region, thus forming a second opening in the first-mentioned opening in the inter-layer insulating

Abstract: A lateral bipolar transistor including a transistor forming region provided on an insulating substrate; a first impurity diffusing region provided on the insulating substrate on one side of the transistor forming region; an emitter region formed in a first portion of the transistor forming region adjacent to the first impurity diffusing region, the emitter region being formed by diffusing a first conduction type of impurity from the first impurity diffusing region into the first portion of the transistor forming region; a base region formed in a second portion of the transistor forming region adjacent to the emitter region, the base region being formed by diffusing a second conduction type of impurity from the first impurity diffusing region into the second portion of the transistor forming region; and a collector region formed in a third portion of the transistor forming region adjacent to the base region. Accordingly, a base width can be reduced, and a dimensional accuracy of the base width can be improved.

Abstract: A bipolar transistor including a semiconductor layer formed on a semiconductor substrate; a base region formed at an upper portion of the semiconductor layer; a graft base region formed at the upper portion of the semiconductor layer so as to connect with a periphery of the base region; an emitter region formed at an upper portion of the base region; an offset insulating film formed on the base region around the emitter region; a collector buried region formed in the semiconductor layer below the base region; a collector drawn region formed in the semiconductor layer so as to connect with the collector buried region and be arranged on the side of the base region adjacent to an element isolating region; an emitter electrode formed on the offset insulating film so as to connect with the emitter region; an emitter insulating film formed so as to cover the emitter electrode; a base electrode formed so as to connect with the graft base region and contact with the emitter insulating film; and a collector electrode

Abstract: The present invention is directed to a method of manufacturing a semiconductor device which comprises the steps of forming an opening portion through a polycide film and an insulating film sequentially formed on a semiconductor substrate of a first conductivity type so as to expose the semiconductor substrate, forming an insulating film on the side surface of the opening portion and the surface of the semiconductor substrate implanting an ion of a second conductivity type into the semiconductor substrate through the insulating film, and forming an insulating side wall in the opening portion. Thus, a metal pollution or the like in the active region due to a metal included in the polycide film can be prevented and a semiconductor device of high performance and high reliability can be manufactured.