Patents by Inventor Hiroyuki Mizuno

Hiroyuki Mizuno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150380768
    Abstract: The objective of the present invention is to provide an electrolyte solution of which electrolyte salt concentration is high and by which cycle characteristics hardly deteriorate and battery lifetime can be extended, and a lithium ion secondary battery which contains the above electrolyte solution. The electrolyte solution of the present invention comprises an electrolyte salt and a solvent, wherein a concentration of the electrolyte salt is more than 1.1 mol/L, the electrolyte salt contains a compound represented by the following formula (1): (XSO2) (FSO2)NLi (1) (wherein X is a fluorine atom, a C1-6 alkyl group or a C1-6 fluoroalkyl group), and the solvent contains a cyclic carbonate.
    Type: Application
    Filed: February 18, 2014
    Publication date: December 31, 2015
    Inventors: Hiroyuki MIZUNO, Kazuhisa HIRATA, Takeo KAWASE, Izuho OKADA, Hiromoto KATSUYAMA, Miwako TOMINAGA, Masayuki OKAJIMA
  • Publication number: 20150371698
    Abstract: A motherboard includes a main wiring as a transmission line for a signal transmitted by a memory controller, and a branching wiring branched from a branching point of the main wiring and connected to the memory device. Furthermore, the motherboard includes a branching wiring including a land to which a memory device may be joined and branched from a branching point, and an open stub formed extending from the land. According to such a structure, ringing in the waveform of a signal received by the receiving circuit may be suppressed at the time of both single-side mounting and double-side mounting, and also, ringing of a signal may be sufficiently suppressed in the case where the number of DIMMs used by the same substrate is changed.
    Type: Application
    Filed: June 10, 2015
    Publication date: December 24, 2015
    Inventor: Hiroyuki Mizuno
  • Publication number: 20150357248
    Abstract: The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.
    Type: Application
    Filed: August 17, 2015
    Publication date: December 10, 2015
    Inventors: Nozomu MATSUZAKI, Hiroyuki MIZUNO, Masashi HORIGUCHI
  • Patent number: 9194033
    Abstract: A chemical composition includes, in mass percent, C: 0.30 to 0.55%, Si: 0.05 to 1.0%, Mn: 0.05 to 0.9%, P: 0.001 to 0.030%, S: 0.005 to 0.12%, Cr: 0.05 to 2.0%, Al: 0.005 to 0.05%, N: 0.0050 to 0.0200%, and the balance being Fe and unavoidable impurities, an amount of N in solid solution being not less than 0.0020%, wherein the contents of Mn and S satisfy relationships expressed by the following expressions: 2.6?Mn/S<15??(1) and Mn+6S<1.2??(2).
    Type: Grant
    Filed: March 27, 2013
    Date of Patent: November 24, 2015
    Assignee: AICHI STEEL CORPORATION
    Inventors: Komei Makino, Hiroyuki Mizuno
  • Publication number: 20150324482
    Abstract: A decision-making support system which is a client-server system comprising: multiple servers; a client having a display; a network; and a database. On the basis of data acquisition conditions supplied via the client the multiple servers acquire from the data base on multiple distributed processing platforms, a first data group spanning from the past to the present, and generate a first network graph for the time from the past to the present. The multiple servers also execute multiple simulations based on the first data group, on the basis of provided simulation conditions, and generate second and third network graphs for a time not included in the first data group or for the future. The client receives the results of the generation of these network graphs and displays on the display the first through third network graphs spanning from the past to the present, and to the future, thereby providing the user with a scenario map.
    Type: Application
    Filed: November 29, 2012
    Publication date: November 12, 2015
    Applicant: Hitachi, Ltd
    Inventors: TAKESHI KATO, Koji FUKUDA, Masaki HAMAMOTO, Yasuyuki KUDO, Hiroyuki MIZUNO
  • Patent number: 9180774
    Abstract: In a work vehicle, a second processing device, disposed over a hydraulic pump, is configured to process the hydraulic gas from an engine. A first processing device is disposed closer to the engine than the second processing device is. Further, the first processing device is positioned higher the second processing device. The first processing device is partially overlapped with the second processing device in a top plan view.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: November 10, 2015
    Assignee: KOMATSU LTD.
    Inventors: Hiroyuki Mizuno, Tomomi Ueda
  • Publication number: 20150319845
    Abstract: A main wire 111 has inner layer wiring patterns 161 to 165 which are wired on an inner layers 114 and 115 connected by via conductors 166 to 169 in series. In addition, a main wire 112 has inner layer wiring patterns 181 to 185 which are wired on the inner layers 114 and 115 connected by via conductors 186 to 189. The inner layer wiring patterns 161 to 165 and the inner layer wiring patterns 181 to 185 are wired so as to change the layer to the inner layer on the opposite side to each other. Branch wires 1211 to 1214 and 1221 to 1224 are branched from the via conductors 166 to 169 and 186 to 189, respectively. Thereby, the present invention provides an inexpensive printed wiring board which can reduce ringing without upsizing the printed wiring board.
    Type: Application
    Filed: November 14, 2013
    Publication date: November 5, 2015
    Inventors: Takashi Numagi, Hikaru Nomura, Masanori Kikuchi, Hiroyuki Mizuno
  • Publication number: 20150295572
    Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.
    Type: Application
    Filed: June 23, 2015
    Publication date: October 15, 2015
    Inventors: Yusuke KANNO, Hiroyuki MIZUNO, Yoshihiko YASU, Kenji HIROSE, Takahiro IRITA
  • Patent number: 9151630
    Abstract: Evaluation indication systems, methods, and programs display a current position of a vehicle and a map around the current position on a display unit, acquire current evaluations that indicate evaluations of fuel consumption in current travel of the vehicle by unit sections, and acquire previous evaluations that indicate evaluations of fuel consumption of the vehicle in a past prior to the current travel by unit sections. The systems, methods, and programs indicate the current evaluations and the previous evaluations together by unit sections on the map.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: October 6, 2015
    Assignee: AISIN AW CO., LTD.
    Inventors: Naoki Miura, Junichi Nonomura, Junki Yamakawa, Hiroyuki Mizuno
  • Patent number: 9146131
    Abstract: Evaluation indication systems, methods, and programs are provided for a hybrid vehicle that is configured to travel in an HV mode with an internal combustion engine or in an EV mode without the internal combustion engine. The systems, methods, and programs display a current position of the hybrid vehicle on a map, acquire current evaluations of fuel consumption of the hybrid vehicle in current travel by unit sections, acquire previous evaluations of fuel consumption of the hybrid vehicle in previous travel by unit sections, and indicate current evaluation icons on the map, each of the icons being an EV icon or an HV icon. Each EV icon indicates that the hybrid vehicle has travelled within the corresponding unit section in the EV mode and each HV icon indicates that the hybrid vehicle has travelled within the corresponding unit section in the HV mode.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: September 29, 2015
    Assignee: AISIN AW CO., LTD.
    Inventors: Naoki Miura, Junichi Nonomura, Junki Yamakawa, Hiroyuki Mizuno
  • Patent number: 9134253
    Abstract: According to one embodiment, an inspecting apparatus is provided with a contact position obtaining unit and an inspection status determining unit. The contact position obtaining unit obtains, by using an inspection result of whether there is a particle on an inspection surface of a holding object and coordinate information of a convex portion in an electrostatic chuck holding mechanism, a contact position of the inspection surface with the convex portion. The inspection status determining unit determines whether a size of the particle adhering to a contact region with the convex portion of the inspection surface is within an allowable range by using a first determining criterion value and determines whether the size of the particle adhering to a non-contact region with the convex portion of the inspection surface is within an allowable range by using a second determining criterion value larger than the first determining criterion value.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: September 15, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Suzuki, Hiroyuki Mizuno
  • Patent number: 9111909
    Abstract: The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: August 18, 2015
    Assignee: Tessera Advanced Technologies, Inc.
    Inventors: Nozomu Matsuzaki, Hiroyuki Mizuno, Masashi Horiguchi
  • Patent number: 9087818
    Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: July 21, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Takahiro Irita
  • Publication number: 20150159247
    Abstract: A chemical composition includes, in mass percent, C: 0.30 to 0.55%, Si: 0.05 to 1.0%, Mn: 0.05 to 0.9%, P: 0.001 to 0.030%, S: 0.005 to 0.12%, Cr: 0.05 to 2.0%, Al: 0.005 to 0.05%, N: 0.0050 to 0.0200%, and the balance being Fe and unavoidable impurities, an amount of N in solid solution being not less than 0.0020%, wherein the contents of Mn and S satisfy relationships expressed by the following expressions: 2.6?Mn/S<15??(1) and Mn+6S<1.2??(2).
    Type: Application
    Filed: March 27, 2013
    Publication date: June 11, 2015
    Inventors: Komei Makino, Hiroyuki Mizuno
  • Patent number: 8994314
    Abstract: An injection molding machine according to the invention includes a motor, a driver circuit that drives the motor; and a rectifying part that supplies electric power to the driver circuit. A regenerative line for regenerative electric power of the motor is connected to the rectifying part in parallel. A converting part and a harmonics component reducing part are provided in the regenerative line. The converting part converts direct electric power between the driver circuit and the rectifying part into alternating electric power which is input to the harmonics component reducing part.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: March 31, 2015
    Assignee: Sumitomo Heavy Industries, Ltd.
    Inventors: Atsushi Kato, Hiroshi Morita, Hiroyuki Mizuno, Noritaka Okada
  • Patent number: 8994313
    Abstract: An injection molding machine includes a motor; a driver circuit; a rectifying part; a capacitor provided between the driver circuit and the rectifying part; a bridge circuit that converts direct electric power between the driver circuit and the rectifying part into alternating electric power; a harmonics component reducing part connected to an alternating side of the bridge circuit; and a regenerative line connected to the rectifying part in parallel, wherein the bridge circuit and the harmonics component reducing part are provided in the regenerative line, and plural switching elements of the bridge circuit are turned on or off such that electric power of the motor is regenerated when a voltage of the capacitor is greater than or equal to a predetermined value, and all the switching elements are turned off when the voltage of the capacitor is less than the predetermined value.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: March 31, 2015
    Assignee: Sumitomo Heavy Industries, Ltd.
    Inventors: Noritaka Okada, Hiroshi Morita, Hiroyuki Mizuno, Atsushi Kato
  • Publication number: 20150062570
    Abstract: According to one embodiment, an inspecting apparatus is provided with a contact position obtaining unit and an inspection status determining unit. The contact position obtaining unit obtains, by using an inspection result of whether there is a particle on an inspection surface of a holding object and coordinate information of a convex portion in an electrostatic chuck holding mechanism, a contact position of the inspection surface with the convex portion. The inspection status determining unit determines whether a size of the particle adhering to a contact region with the convex portion of the inspection surface is within an allowable range by using a first determining criterion value and determines whether the size of the particle adhering to a non-contact region with the convex portion of the inspection surface is within an allowable range by using a second determining criterion value larger than the first determining criterion value.
    Type: Application
    Filed: January 29, 2014
    Publication date: March 5, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masaru SUZUKI, Hiroyuki Mizuno
  • Publication number: 20140349219
    Abstract: According to embodiments, an exposure method is provided. In the exposure method, a transmittance of a pellicle is adjusted every position of a mask pattern included in a reflection type mask. And when adjusting the transmittance of the pellicle, a film thickness of the pellicle is adjusted on the basis of a transmittance correction amount. Thereafter, exposure is conducted onto a substrate by using the reflection type mask with the pellicle stuck thereon.
    Type: Application
    Filed: November 25, 2013
    Publication date: November 27, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki MIZUNO, Yosuke Okamoto, Takeshi Koshiba, Satoshi Nagai
  • Publication number: 20140252495
    Abstract: The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.
    Type: Application
    Filed: February 10, 2014
    Publication date: September 11, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Nozomu MATSUZAKI, Hiroyuki MIZUNO, Masashi HORIGUCHI
  • Patent number: 8829968
    Abstract: A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.
    Type: Grant
    Filed: September 8, 2009
    Date of Patent: September 9, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroyuki Mizuno, Yusuke Kanno, Kazumasa Yanagisawa, Yoshihiko Yasu, Nobuhiro Oodaira