Patents by Inventor Hiroyuki Shigeta
Hiroyuki Shigeta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11942495Abstract: A semiconductor device includes a semiconductor chip, a circuit board, a heat releasing plate, an adhesive member, and a conductive member. The circuit board transmits a signal of the semiconductor chip. The heat releasing plate has the semiconductor chip disposed thereon, and has an opening in a region on the outer side of a semiconductor chip placement region that is a region in which the semiconductor chip is disposed. The adhesive member is disposed in a region on the outer side of the opening on a different surface of the heat releasing plate from the surface on which the semiconductor chip is disposed, and bonds the circuit board and the heat releasing plate to each other. The conductive member connects the semiconductor chip and the circuit board to each other via the opening.Type: GrantFiled: June 21, 2019Date of Patent: March 26, 2024Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Daisuke Chino, Hiroyuki Shigeta, Shigekazu Ishii, Koyo Hosokawa, Hirohisa Yasukawa, Mitsuhito Kanatake, Kosuke Hareyama, Yutaka Ootaki, Kiyohisa Sakai, Atsushi Tsukada, Hirotaka Kobayashi, Ninao Sato, Yuki Yamane
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Publication number: 20230298955Abstract: A region of a sealing part is effectively utilized. -A semiconductor device includes a semiconductor element, a substrate, a sealing part, and a cavity region. The substrate included in this semiconductor device is disposed adjacent to a bottom surface of the semiconductor element. The sealing part included in this semiconductor device is formed in a shape that covers an upper surface that is a surface facing the bottom surface of the semiconductor element, and seals the semiconductor element. The cavity region included in this semiconductor device is a region disposed in the sealing part and formed with a cavity.Type: ApplicationFiled: March 5, 2021Publication date: September 21, 2023Applicants: SONY GROUP CORPORATION, SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Shigekazu ISHII, Bernadette ELLIOTT-BOWMAN, Christopher WRIGHT, Timothy BEARD, Matthew LAWRENSON, Hirotaka KOBAYASHI, Hiroyuki SHIGETA
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Publication number: 20230125605Abstract: Provided is a semiconductor device capable of maintaining the flatness of a glass substrate and sufficiently protecting an end portion of the glass substrate. A semiconductor device according to one aspect of the present disclosure includes: a glass substrate including a first surface, a second surface opposite to the first surface, and a first side surface between the first surface and the second surface; wirings provided on the first and second surfaces; a first insulating film that covers the first surface; a second insulating film that covers the second surface; and a third insulating film that covers the first side surface, the third insulating film being continuous with at least one of the first and second insulating films.Type: ApplicationFiled: March 23, 2021Publication date: April 27, 2023Inventors: YUTO TANAKA, SHUICHI OKA, SHUN MITARAI, KIWAMU ADACHI, TAKAHIRO IGARASHI, HIIZU OHTORII, NAOKI KAKOIYAMA, KOUSUKE SEKI, HIROYUKI SHIGETA
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Publication number: 20220262841Abstract: Circuits are added while an increase in size of a semiconductor package is prevented. The semiconductor package includes a transparent member; an embedding resin; an embedded circuit; and a solid-state image pickup element. In the semiconductor package, the embedding resin is formed around the transparent member. Further, in the semiconductor package, the embedded circuit is embedded in the embedding resin. Further, in the semiconductor package, the solid-state image pickup element performs photoelectric conversion on light that has passed through the transparent member and thereby generates image data.Type: ApplicationFiled: May 22, 2020Publication date: August 18, 2022Inventors: HIROYUKI SHIGETA, KOHYOH HOSOKAWA, JO UMEZAWA, MASAKI HATANO, HIROFUMI MAKINO, TOSHIKI KOYAMA
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Publication number: 20220139979Abstract: An improvement in heat radiation efficiency is achieved. A semiconductor device according to the present technology includes a substrate portion on which a semiconductor chip is mounted and in which an external connection terminal for performing electrical connection to the outside is formed on a rear surface on a side opposite to a front surface which is a surface on a side where the semiconductor chip is mounted, an outer wall portion that protrudes toward the front surface side in an outer circumferential portion of the substrate portion, a lid portion which is supported by the outer wall portion and covers the semiconductor chip, and a heat storage member which is disposed at a position further inside than the outer wall portion between the rear surface of the substrate portion and a rear surface of the lid portion.Type: ApplicationFiled: January 5, 2020Publication date: May 5, 2022Inventors: TSUYOSHI WATANABE, HIROKAZU NAKAYAMA, HIROYUKI SHIGETA, HITOSHI SHIBUE, HIROTAKA KOBAYASHI, KOSUKE HAREYAMA
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Publication number: 20210233949Abstract: Deformation of a semiconductor chip is to be prevented in a semiconductor device in which a heat releasing plate and a circuit board are disposed. The semiconductor device includes the semiconductor chip, the circuit board, the heat releasing plate, an adhesive member, and a conductive member. The circuit board transmits a signal of the semiconductor chip. The heat releasing plate has the semiconductor chip disposed thereon, and has an opening in a region on the outer side of a semiconductor chip placement region that is a region in which the semiconductor chip is disposed. The adhesive member is disposed in a region on the outer side of the opening on a different surface of the heat releasing plate from the surface on which the semiconductor chip is disposed, and bonds the circuit board and the heat releasing plate to each other. The conductive member connects the semiconductor chip and the circuit board to each other via the opening.Type: ApplicationFiled: June 21, 2019Publication date: July 29, 2021Inventors: DAISUKE CHINO, HIROYUKI SHIGETA, SHIGEKAZU ISHII, KOYO HOSOKAWA, HIROHISA YASUKAWA, MITSUHITO KANATAKE, KOSUKE HAREYAMA, YUTAKA OOTAKI, KIYOHISA SAKAI, ATSUSHI TSUKADA, HIROTAKA KOBAYASHI, NINAO SATO, YUKI YAMANE
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Patent number: 10714402Abstract: This semiconductor chip package has opposed first surface and second surface, and includes a semiconductor chip having a circuit part and an electrode for supplying a voltage to the circuit part, a resin layer formed in a periphery of the semiconductor chip, a substrate that is disposed to face the first surface of the semiconductor chip and the resin layer, and a plurality of external terminals that are provided on the second surface of the semiconductor chip, each of the plurality of external terminals being electrically coupled to any of the plurality of electrodes.Type: GrantFiled: May 16, 2017Date of Patent: July 14, 2020Assignee: SONY CORPORATIONInventors: Hiroyuki Shigeta, Yuuji Nishitani
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Publication number: 20190139843Abstract: This semiconductor chip package has opposed first surface and second surface, and includes a semiconductor chip having a circuit part and an electrode for supplying a voltage to the circuit part, a resin layer formed in a periphery of the semiconductor chip, a substrate that is disposed to face the first surface of the semiconductor chip and the resin layer, and a plurality of external terminals that are provided on the second surface of the semiconductor chip, each of the plurality of external terminals being electrically coupled to any of the plurality of electrodes.Type: ApplicationFiled: May 16, 2017Publication date: May 9, 2019Inventors: HIROYUKI SHIGETA, YUUJI NISHITANI
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Patent number: 9170841Abstract: A multiprocessor system includes a plurality of processors, each including a task scheduler that determines a task execution order of tasks in a task set to be executed by the processors within a task period which is defined as a period in repeated execution of the task sets; and a scheduler management device having a command unit configured to issue a command for at least one of the task schedulers to change the task execution order, wherein each of the at least one of the task schedulers, when receiving the command from the command unit, changes the task execution order of the corresponding processor.Type: GrantFiled: December 18, 2012Date of Patent: October 27, 2015Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Kiyokazu Fukuzaki, Masanori Henmi, Hazuki Okabayashi, Hiroyuki Murata, Takatsugu Sawai, Hiroyuki Shigeta
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Patent number: 6319749Abstract: In a lead frame with a reinforcing ring surrounding a semiconductor element which are electrically connected to leads through electrodes is integrally formed through suspending portions, reinforcing portions for reinforcing the suspending portions are provided on the suspending portions. Upon application of a lead frame forming technique in which a laminate plate of three or more layers is used as a base, and inner leads are formed at one side while outer leads are formed by the surface layer at the other side, the lead frame is formed by forming a ring in place of outer leads, for example. A semiconductor package is formed by mounting the lead frame on a semiconductor chip.Type: GrantFiled: May 2, 2000Date of Patent: November 20, 2001Assignee: Sony CorporationInventors: Hiroyuki Shigeta, Kenji Osawa, Kazuhiro Sato, Haruhiko Makino, Makoto Ito
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Patent number: 6107678Abstract: In a lead frame with a reinforcing ring surrounding a semiconductor element which are electrically connected to leads through electrodes is integrally formed through suspending portions, reinforcing portions for reinforcing the suspending portions are provided on the suspending portiones. Upon application of a lead frame forming technique in which a laminate plate of three or more layers is used as a base, and inner leads are formed at one side while outer leads are formed by the surface layer at the other side, the lead frame is formed by forming a ring in place of outer leads, for example. A semiconductor package is formed by mounting the lead frame on a semiconductor chip.Type: GrantFiled: August 12, 1997Date of Patent: August 22, 2000Assignee: Sony CorporationInventors: Hiroyuki Shigeta, Kenji Osawa, Kazuhiro Sato, Haruhiko Makino, Makoto Ito
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Patent number: 6054773Abstract: An adhesive sheet which has rigidity and a portion which adheres to the back surface of the outside portion of the film circuit is used. Specifically, there is used the adhesive sheet which is obtained by forming cushioning adhesive sheet layers on both the surfaces of the rigid sheet layer formed of stainless or the like. Further, the rigid sheet layer is also used for electrostatic shield. The co-planarity of external terminals (soldering balls) is enhanced without vainly increasing the weight of a semiconductor device, and further the resistance to high-frequency noses in the semiconductor device is enhanced.Type: GrantFiled: March 27, 1998Date of Patent: April 25, 2000Assignee: Sony CorporationInventors: Kenji Ohsawa, Kazuhiro Sato, Hiroyuki Shigeta
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Patent number: 5812381Abstract: A lead frame includes a base member having a device hole for accommodating a semiconductor chip therein, a plurality of inner lead portions extended outward from respective sides of the device hole, outer lead portions electrically connected to the inner lead portions, respectively, an adhesion area to which the inner lead portions formed on the base member are adhered, and a plurality of dummy leads disposed on a portion of the adhesion area where a density of the inner lead portions is low.Type: GrantFiled: August 8, 1996Date of Patent: September 22, 1998Assignee: Sony CorporationInventors: Hiroyuki Shigeta, Mutsumi Nagano