Abstract: An optical disc player enters a sleep (low power consumption) mode when inactive for a predetermined time. The optical disc player includes a buffer RAM for storing index information read from a disc. A refresh circuit is connected to the buffer RAM to refresh the RAM. The refresh circuit includes a reference clock generator which generates a reference clock signal having a predetermined frequency from a reference clock using an oscillator. When the disc player enters the sleep mode, it issues a stop signal to the reference clock generator, which then stops generating the reference clock signal and produces a sleep mode clock signal having a frequency necessary to refresh the buffer RAM. A refresh signal generator circuit connected to the reference clock generator produces a refresh signal for the buffer RAM using the sleep mode clock signal.

Abstract: A low-cost controller that operates in accordance with firmware stored in a memory. The controller includes a data processing circuit that performs predetermined processing on data and generates processed data. A write wire is connected to the memory, and a terminal is provided for use in the output of the data processed by the data processing circuit and/or the provision of the data to the data processing circuit. The controller includes a selector for connecting the write wire and the terminal to write the firmware to the memory.

Abstract: A system for providing an information-provided vehicle equipped with a navigation system with traffic information, the system capable of providing the vehicle with the traffic information reflecting the real traffic condition in each traveling direction even if the vehicle travels in either branch direction in a branch point area including the branch point. It comprises a traffic information server 1 and the traffic information server 1 includes a means 21 for collecting information on the time required for traveling in the branch point area, which is composed of an pre-branch route and a plurality of post-branch routes branching off from the pre-branch route at the branch point, from an information providing vehicle 3b and a means 22 for generating information on the time required for traveling in each traveling direction in the branch point area on the basis of the information.

Abstract: An optical disc player enters a sleep (low power consumption) mode when inactive for a predetermined time. The optical disc player includes a buffer RAM for storing index information read from a disc. A refresh circuit is connected to the buffer RAM to refresh the RAM. The refresh circuit includes a reference clock generator which generates a reference clock signal having a predetermined frequency from a reference clock using an oscillator. When the disc player enters the sleep mode, it issues a stop signal to the reference clock generator, which then stops generating the reference clock signal and produces a sleep mode clock signal having a frequency necessary to refresh the buffer RAM. A refresh signal generator circuit connected to the reference clock generator produces a refresh signal for the buffer RAM using the sleep mode clock signal.

Abstract: An optical disc player enters a sleep (low power consumption) mode when inactive for a predetermined time. The optical disc player includes a buffer RAM for storing index information read from a disc. A refresh circuit is connected to the buffer RAM to refresh the RAM. The refresh circuit includes a reference clock generator which generates a reference clock signal having a predetermined frequency from a reference clock using an oscillator. When the disc player enters the sleep mode, it issues a stop signal to the reference clock generator, which then stops generating the reference clock signal and produces a sleep mode clock signal having a frequency necessary to refresh the buffer RAM. A refresh signal generator circuit connected to the reference clock generator produces a refresh signal for the buffer RAM using the sleep mode clock signal.

Abstract: A decoder for decreasing the load on a microcomputer. The decoder stores in a buffer memory in sector units digital data. The decoder includes a check head register for storing a first address of the buffer memory when storing the processed digital data in the buffer memory. A check sector counter counts the number of sectors of the processed digital data stored in the buffer memory to generate a count value. A command decision circuit decides whether digital data requested to be transferred is stored in the buffer memory based on the first address, the count value, and a head address of the digital data. The command decision circuit permits the decoder to transfer the processed digital data when deciding that the digital data requested to be transferred is stored in the buffer memory.

Abstract: A vehicle navigation server for providing traffic information, which is useful and has a suitable data amount, to a vehicle navigation device, so as to make the vehicle have a comfortable travel. The server calculates at least one proposed travel based on input data including a current or start position and a destination of the vehicle, and defines a map mesh consisting of mesh units on the proposed travel route. The server extracts traffic information relating to each mesh unit from a traffic information storage device in turn, where traffic information relating to the mesh unit which includes the start or current position is obtained first. The server monitors a total amount of extracted information, and terminates information extraction for the following mesh units when the total amount becomes equal to or larger than a predetermined value. The server then sends the traffic information to a vehicle navigation device.

Abstract: A CD-ROM decoder that performs code error correction and/or code error detection on digital data partitioned in sectors having a certain format includes a circuit for reading and analyzing the header information stored with each sector of CD-ROM data, which relieves a control microprocessor of having to perform such task. A header information register stores the header information for each sector of data. A sector information conversion circuit connected to the header information register determines the specific format of the sector data and generates corresponding sector information. The sector data and the corresponding sector information are stored in a buffer memory.

Abstract: A vehicle navigation server for providing traffic information, which is useful and has a suitable data amount, to a vehicle navigation device, so as to make the vehicle have a comfortable travel. The server calculates at least one proposed travel based on input data including a current or start position and a destination of the vehicle, and defines a map mesh consisting of mesh units on the proposed travel route. The server extracts traffic information relating to each mesh unit from a traffic information storage device in turn, where traffic information relating to the mesh unit which includes the start or current position is obtained first. The server monitors a total amount of extracted information, and terminates information extraction for the following mesh units when the total amount becomes equal to or larger than a predetermined value. The server then sends the traffic information to a vehicle navigation device.

Abstract: A vehicle navigation system for selecting a suitable travel route based on transmitted traffic information. A server calculates a proposed travel route based on input data and defines communication points so as to newly extract traffic information for an area from each communication point to the destination from a traffic information storage device, where a point from which a detour around a place noted in the traffic information is included. The server stores data for identifying the registrant, the proposed travel route, and the communication points in a storage device and sends the traffic information and communication points to a vehicle navigation device. The sent traffic information includes detailed information about a section from the current or start position of the vehicle to the closest communication point to the vehicle on the way to the destination and simplified information about a section from this point to the destination.

Abstract: A CD-ROM decoder for decreasing the load on a microcomputer. The CD-ROM decoder stores in a buffer memory in sector units digital data. The CD-ROM decoder includes a check head register for storing a first address of the buffer memory when storing the processed digital data in the buffer memory. A check sector counter counts the number of sectors of the processed digital data stored in the buffer memory to generate a count value. A command decision circuit decides whether digital data requested to be transferred is stored in the buffer memory based on the first address, the count value, and a head address of the digital data. The command decision circuit permits the CD-ROM decoder to transfer the processed digital data when deciding that the digital data requested to be transferred is stored in the buffer memory.

Abstract: A code error correcting and detecting apparatus includes a controller that repetitively processes error correction and detection of encoded CD-ROM data, thereby relieving a control microprocessor of a CD-ROM system of the burden associated with such repetitive processing. The apparatus includes an error correction circuit that performs code error correction on digital data, such as digital data read from a CD, using an error-correcting code (ECC). An error detection circuit performs error detection on the error-corrected digital data using an error-detecting code (EDC) and determines whether there is an error. A control circuit causes the error-correction circuit to repeat its error-correction processing in accordance with the detection of an error by the error detection circuit.

Abstract: A small multichip module has a mother chip and a stack chip. The stack chip is stacked on the mother chip. The mother chip includes a first bonding pad located in a circuit area. A bonding pad of the stack chip is wire-bonded with the bonding pad of the mother chip.

Abstract: The present invention provides a human c-Ha-ras proto-oncogene transgenic rat and the methods of the screening of many carcinogens and the screenings of promoters of carcinogenesis and preventive and inhibitory agents of tumors, and additionally enables the analysis of the carcinogenesis mechanism of a number of tumors.

Abstract: An optical signal processing apparatus includes a first optical waveguide and a first slab waveguide configured to equally distribute an output light of the first optical waveguide. A first arrayed waveguide includes an aggregate of optical waveguides changing in optical length by a constant interval for dividing the output light. A second slab waveguide focuses the optical output of the first arrayed waveguide. A spatial filter receives incident light focused by the second slab waveguide and distributes the incident light on a straight line. The spatial filter also modulates the light into a desired amplitude according to the position on the straight line. The apparatus also includes a second arrayed waveguide and an aggregate of optical waveguides changing in optical length by a constant interval for applying light modulated by the spatial filter to the second arrayed waveguide. Structure is provided for converging the output light of said second arrayed waveguide to a single point.

Abstract: A small multichip module has a mother chip and a stack chip. The stack chip is stacked on the mother chip. The mother chip includes a first bonding pad located in a circuit area. A bonding pad of the stack chip is wire-bonded with the bonding pad of the mother chip.

Abstract: A code error correcting apparatus, which can be used in a CD digital audio system, reads data stored on a disc, performs error correction, and transfers the error corrected data to another device, such as a computer, at an increased playback speed. The apparatus includes a digital processor which receives and processes (EFM demodulation) the data read from the disc, and a latch circuit connected to the processor for receiving the processed data. A memory is connected to the latch circuit by way of an input interface circuit, for storing the latched data. An error correction circuit connected to the memory reads the stored data, performs error correction on the data, and stores the error corrected data back in the memory. An output interface circuit is connected to the memory and provides an interface to the memory for external devices. The digital processor, the latch circuit, the input interface and the error correction circuit are all formed on a single substrate.

Abstract: A low-cost controller that operates in accordance with firmware stored in a memory. The controller includes a data processing circuit that performs predetermined processing on data and generates processed data. A write wire is connected to the memory, and a terminal is provided for used in the output of the data processed by the data processing circuit and/or the provision of the data to the data processing circuit. The controller includes a selector for connecting the write wire and the terminal to write the firmware to the memory.

Abstract: A CD-ROM decoder that reduces the load on a microcomputer temporarily stores in a buffer memory in sector units digital data having a predetermined number of bytes and a predetermined format. The CD-ROM also processes the digital data by correcting and detecting code errors included in the digital data. Further, the CD-ROM decoder transfers the processed digital data. The CD-ROM decoder includes a command register for storing a data transfer request command that includes format information of transfer request data and a data transfer circuit connected to the command register. The data transfer circuit decides the format information of the data transfer request command and determines the byte number of the processed digital data that is to be transferred. Further, the data transfer circuit reads the processed digital data from the buffer memory based on the determined byte number and transfers the read processed digital data.

Abstract: A CD-ROM decoder that reduces the load on a microcomputer temporarily stores in a buffer memory in sector units digital data having a predetermined number of bytes and a predetermined format. The CD-ROM decoder also processes the digital data by selectively correcting and detecting code errors included in the digital data. A sector information conversion circuit identifies a mode of a sector of the digital data based on header information and compares former four bytes and latter four bytes of sub-header information to identify a form of the sector of the digital data.