Patents by Inventor Hisakatsu Araki

Hisakatsu Araki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SIGNAL TRANSMISSION SYSTEM FOR TRANSMITTING SIGNALS BETWEEN LSI CHIPS, RECEIVER CIRCUIT FOR USE IN THE SIGNAL TRANSMISSION SYSTEM, AND SEMICONDUCTOR MEMORY DEVICE APPLYING THE SIGNAL TRANSMISSION SYSTEM
    Patent number: 6493394
    Abstract: A signal transmission system has a response time of a signal transmission line which is set approximately equal to or longer than the length of a transmitted symbol. More specifically, terminal resistance is set larger than the characteristic impedance of the signal transmission line, driver output resistance is set to a large value, or a damping resistor is provided in series with the signal transmission line. With this configuration, signal power can be reduced drastically.
    Type: Grant
    Filed: February 19, 2002
    Date of Patent: December 10, 2002
    Assignee: Fujitsu Limited
    Inventors: Hirotaka Tamura, Miyoshi Saito, Kohtaroh Gotoh, Shigetoshi Wakayama, Junji Ogawa, Hisakatsu Araki, Tsz-shing Cheung
  • Signal transmission system having a timing adjustment circuit
    Patent number: 6484268
    Abstract: A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core. The timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates the DRAM control signal by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: November 19, 2002
    Assignee: Fujitsu Limited
    Inventors: Hirotaka Tamura, Hisakatsu Araki, Shigetoshi Wakayama, Kohtaroh Gotoh, Junji Ogawa
  • Signal transmission system for transmitting signals between LSI chips, receiver circuit for use in the signal transmission system, and semiconductor memory device applying the signal transmission system
    Publication number: 20020080883
    Abstract: A signal transmission system has a response time of a signal transmission line which is set approximately equal to or longer than the length of a transmitted symbol. More specifically, terminal resistance is set larger than the characteristic impedance of the signal transmission line, driver output resistance is set to a large value, or a damping resistor is provided in series with the signal transmission line. With this configuration, signal power can be reduced drastically.
    Type: Application
    Filed: February 19, 2002
    Publication date: June 27, 2002
    Applicant: FUJITSU LIMITED
    Inventors: Hirotaka Tamura, Miyoshi Saito, Kohtaroh Gotoh, Shigetoshi Wakayama, Junji Ogawa, Hisakatsu Araki, Tsz-shing Cheung
  • SIGNAL TRANSMISSION SYSTEM FOR TRANSMITTING SIGNALS BETWEEN LSI CHIPS, RECEIVER CIRCUIT FOR USE IN THE SIGNAL TRANSMISSION SYSTEM, AND SEMICONDUCTOR MEMORY DEVICE APPLYING THE SIGNAL TRANSMISSION SYSTEM
    Patent number: 6377638
    Abstract: A signal transmission system has a response time of a signal transmission line which is set approximately equal to or longer than the length of a transmitted symbol. More specifically, terminal resistance is set larger than the characteristic impedance of the signal transmission line, driver output resistance is set to a large value, or a damping resistor is provided in series with the signal transmission line. With this configuration, signal power can be reduced drastically.
    Type: Grant
    Filed: October 12, 2000
    Date of Patent: April 23, 2002
    Assignee: Fujitsu Limited
    Inventors: Hirotaka Tamura, Miyoshi Saito, Kohtaroh Gotoh, Shigetoshi Wakayama, Junji Ogawa, Hisakatsu Araki, Tsz-shing Cheung
  • Timing signal generating circuit, semiconductor integrated circuit device and semiconductor integrated circuit system to which the timing signal generating circuit is applied, and signal transmission system
    Publication number: 20010007136
    Abstract: A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core. The timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates the DRAM control signal by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period.
    Type: Application
    Filed: February 28, 2001
    Publication date: July 5, 2001
    Applicant: Fujitsu Limited
    Inventors: Hirotaka Tamura, Hisakatsu Araki, Shigetoshi Wakayama, Kohtaroh Gotoh
  • Timing signal generating circuit, semiconductor integrated circuit device and semiconductor integrated circuit system to which the timing signal generating circuit is applied, and signal transmission system
    Patent number: 6247138
    Abstract: A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core. The timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates the DRAM control signal by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period.
    Type: Grant
    Filed: June 8, 1998
    Date of Patent: June 12, 2001
    Assignee: Fujitsu Limited
    Inventors: Hirotaka Tamura, Hisakatsu Araki, Shigetoshi Wakayama, Kohtaroh Gotoh, Junji Ogawa
  • Signal transmission system for transmitting signals between LSI chips, receiver circuit for use in the signal transmission system, and semiconductor memory device applying the signal transmission system
    Patent number: 6157688
    Abstract: A signal transmission system has a response time of a signal transmission line which is set approximately equal to or longer than the length of a transmitted symbol. More specifically, terminal resistance is set larger than the characteristic impedance of the signal transmission line, driver output resistance is set to a large value, or a damping resistor is provided in series with the signal transmission line. With this configuration, signal power can be reduced drastically.
    Type: Grant
    Filed: October 6, 1997
    Date of Patent: December 5, 2000
    Assignee: Fujitsu Limited
    Inventors: Hirotaka Tamura, Miyoshi Saito, Kohtaroh Gotoh, Shigetoshi Wakayama, Junji Ogawa, Hisakatsu Araki, Tsz-shing Cheung