Patents by Inventor Hisanobu Utsunomiya

Hisanobu Utsunomiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7084501
    Abstract: The wide usable interconnecting component of the present invention is capable of reducing number of components or electric elements and reducing number of interconnecting sections without limiting circuit design. The interconnecting component electrically interconnects electric components, and the interconnecting component acts as an electric element. Namely, the interconnecting component acts as a passive element or an active element.
    Type: Grant
    Filed: April 21, 2004
    Date of Patent: August 1, 2006
    Assignee: Interconnection Technologies Inc.
    Inventor: Hisanobu Utsunomiya
  • Publication number: 20050017344
    Abstract: The wide usable interconnecting component of the present invention is capable of reducing number of components or electric elements and reducing number of interconnecting sections without limiting circuit design. The interconnecting component electrically interconnects electric components, and the interconnecting component acts as an electric element. Namely, the interconnecting component acts as a passive element or an active element.
    Type: Application
    Filed: April 21, 2004
    Publication date: January 27, 2005
    Inventor: Hisanobu Utsunomiya
  • Patent number: 6426468
    Abstract: The circuit board of the present invention makes the length of the conductor patterns shorter and improves the electric performance for the high speed signal processing. The circuit board of the present invention, which comprises a substrate, is characterized in that the substrate includes: a first face on which conductor patterns, which will be connected to a semiconductor chip, are formed; a second face on which a plurality of pads, on which terminals are formed, are matrically formed; and plated through holes whose one end are respectively opened in the conductor patterns and whose the other ends are respectively opened in the pads, wherein inner faces of the plated through holes are coated with plating layers so as to respectively electrically connect the conductor patterns with the pad.
    Type: Grant
    Filed: September 19, 2000
    Date of Patent: July 30, 2002
    Assignee: Kabushiki Kaisha Eastern
    Inventors: Hisanobu Utsunomiya, Tadahisa Tanaka