Abstract: The present invention provides a reconfigurable processing apparatus enabling clusters to utilize a shared functional unit by using data and a validity signal received from the clusters by way of a network therebetween. In the reconfigurable processing apparatus comprising one or more clusters which are reconfigured based on configuration information, the shared functional unit accepts an input data and an input valid signal from the clusters, the input valid signal starts up the shared functional unit so as to operate the input data received with the input valid signal and output, to the cluster, an output data as the operation result and an output valid signal for notifying of the cluster as an output destination of the aforementioned output data.

Abstract: In a method and apparatus for carrying out circuit simulation which performs circuit simulation on a circuit to be simulated, a plurality of partial circuits to be inspected for equivalence in order to check if they exhibit equivalent operational characteristics are extracted from the circuit to be simulated, and the intensity of the influence of an external terminal of the circuit to be simulated is assessed by tracing paths linking the external terminal and given terminals of the partial circuits. Moreover, based on the configurations of the partial circuits, the connectional relationships of corresponding input terminals of the partial circuits, the operational characteristics of corresponding component elements of the partial circuits, and the intensity of the influence of the external terminal, the plurality of partial circuits are inspected for equivalence in order to detect partial circuits exhibiting equivalence.

Abstract: A reconfigurable operation apparatus consists of a plurality of operation units capable of reconfiguring themselves by using a piece of given first configuration data and of operating simultaneously with one another; RAMs; diverse processor elements required for constituting an operation apparatus; an inter-resource network interconnecting the operation units, the RAMs and the diverse processor elements, performing data transfers between resources connected thereto in a uniform transfer time independent of positions and kinds of the resources, and being reconfigurable by using a given second configuration data; and a configuration memory storing the first and the second configuration data. Configuration data is loaded from an external storage apparatus onto the configuration memory, and the first and the second configuration data are supplied to the reconfigurable processor resources in appropriate sequence and timing based on data available from a plurality of operation units.

Abstract: An operation apparatus includes a plurality of operation device units; a configuration memory storing setting information provided for each predetermined state of the plurality of operation device units; and a sequencer controlling the plurality of operation device units by outputting transition destination addresses designating relevant information from configuration information comprising the setting information provided for each state of the operation device units stored in the configuration memory, wherein the sequencer carries out operation based on task information previously loaded and a change-over condition signal output from the plurality of operation device units, and generates the transition destination address to output to the configuration memory.

Abstract: An operation apparatus includes a sequencer controlling states of a plurality of operation devices and a configuration memory storing therein configuration information as setting information for each state in the operation device. In the operation apparatus, a path which requires a data buffer and another path which requires no such a data buffer are provided for inputting data to the operation device, a data buffer control part is provided for controlling selection from these two paths and operation of the data buffer, and contents of path selection and operation control of the data buffer carried out by the data buffer control part are set according to the configuration information.

Abstract: The reconfigurable circuit of the present invention in which time division multiple processing is possible has a pipeline structure with the number of stages of an integral multiple of a given number, and comprises a plurality of processor elements having a processing unit whose configuration is variable according to first configuration data to be supplied, a network in which all inputs and outputs of a plurality of said processor elements are connected and which transfers data by one clock between the input and output according to second configuration data to be supplied, and a switching unit which cyclically switches by one clock and supplies the first and second configuration data prepared for the given number of tasks to each of the processing units.

Abstract: In a method and apparatus for carrying out circuit simulation which performs circuit simulation on a circuit to be simulated, a plurality of partial circuits to be inspected for equivalence in order to check if they exhibit equivalent operational characteristics are extracted from the circuit to be simulated, and the intensity of the influence of an external terminal of the circuit to be simulated is assessed by tracing paths linking the external terminal and given terminals of the partial circuits. Moreover, based on the configurations of the partial circuits, the connectional relationships of corresponding input terminals of the partial circuits, the operational characteristics of corresponding component elements of the partial circuits, and the intensity of the influence of the external terminal, the plurality of partial circuits are inspected for equivalence in order to detect partial circuits exhibiting equivalence.

Abstract: Paths from a block that includes the node that is the object of analysis to another block are searched for by a path search section for all blocks in a circuit; and a depth judgment section finds the depth of each block from that path search information. An effective block judgment section compares the depth of each block to a specified depth that is stored in a specified depth storage section, and judges which blocks are effective blocks. Thus, blocks that include nodes that exert influence on the simulation accuracy at the node that is the object of analysis are extracted from the circuit that is the object of simulation as effective blocks. Then, in the circuit simulation, events are generated only for the effective blocks, and a transient analysis simulation is executed by the event-driven method. This permits the processing speed of the simulation to be increased while maintaining accuracy.