Patents by Inventor Hisao Ise

Hisao Ise has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7187065
    Abstract: A semiconductor device comprises a semiconductor chip which is mounted on a stage. A plurality of leads are electrically connected with the semiconductor chip. A package encloses the semiconductor chip and a part of the plurality of leads. A first corner lead is provided in the stage and outwardly extends from at least one of vertex portions at four corners of the stage to an exterior of the package.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: March 6, 2007
    Assignee: Fujitsu Limited
    Inventor: Hisao Ise
  • Patent number: 7071768
    Abstract: In an integrated circuit having an internal supply voltage generation circuit which generates an internal supply voltage by descending an external supply voltage, there is provided an internal circuit which operates with a supplied internal supply voltage. The internal supply voltage generation circuit changes an internal supply voltage level to be generated in accordance with an operation speed of the internal circuit. Preferably the semiconductor integrated circuit includes a clock control circuit which generates an internal clock signal the frequency of which is controlled in accordance with the operation speed of the internal circuit. When the internal clock signal is controlled to have a higher frequency, the internal supply voltage is controlled to be higher. Also, when the internal clock signal is controlled to have a lower frequency, the internal supply voltage is controlled to be lower.
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: July 4, 2006
    Assignee: Fujitsu Limited
    Inventors: Hiroyuki Abe, Yutaka Takasuka, Hisao Ise, Hiroko Takano, Sachie Takahashi
  • Publication number: 20060060951
    Abstract: A semiconductor device comprises a semiconductor chip which is mounted on a stage. A plurality of leads are electrically connected with the semiconductor chip. A package encloses the semiconductor chip and a part of the plurality of leads. A first corner lead is provided in the stage and outwardly extends from at least one of vertex portions at four corners of the stage to an exterior of the package.
    Type: Application
    Filed: January 14, 2005
    Publication date: March 23, 2006
    Applicant: FUJITSU LIMITED
    Inventor: Hisao Ise
  • Publication number: 20040057324
    Abstract: In an integrated circuit having an internal supply voltage generation circuit which generates an internal supply voltage by descending an external supply voltage, there is provided an internal circuit which operates with a supplied internal supply voltage. The internal supply voltage generation circuit changes an internal supply voltage level to be generated in accordance with an operation speed of the internal circuit. Preferably the semiconductor integrated circuit includes a clock control circuit which generates an internal clock signal the frequency of which is controlled in. accordance with the operation speed of the internal circuit. When the internal clock signal is controlled to have a higher frequency, the internal supply voltage is controlled to be higher. Also, when the internal clock signal is controlled to have a lower frequency, the internal supply voltage is controlled to be lower.
    Type: Application
    Filed: July 29, 2003
    Publication date: March 25, 2004
    Inventors: Hiroyuki Abe, Yutaka Takasuka, Hisao Ise, Hiroko Takano, Sachie Takahashi
  • Patent number: 6281580
    Abstract: A face up BGA package has a plurality of terminals and lead pads on a package substrate. Connecting some of the terminals to their corresponding lead pads via nonconnection terminals when changing the size of a chip mounted on the package substrate makes it possible to connect all necessary terminals and lead pads by using inner leads without short circuiting the inner leads and without shortage of space in which to wire the inner leads.
    Type: Grant
    Filed: March 24, 1999
    Date of Patent: August 28, 2001
    Assignee: Fujitsu Limited
    Inventors: Hisao Ise, Hitoshi Takahashi