Abstract: A low frequency detector circuit includes a differential input that is received by an offset comparator circuit. The offset comparator circuit provides respective output signals COMPX and COMPY which can be compared to a generated threshold voltage Vcomp by an E2C (ECL to CMOS) comparators. The outputs of the E2C comparators are used by respective timers to generate fault signals. In addition to detecting low frequency conditions, common voltage conditions can be detected as well and can be distinguished at very high frequency conditions.

Abstract: The present invention comprises a pair of circuits (171, 172) within the first stage (100) of an AC signal pre-amplifier. The present invention reduces the current mismatch at the base of the first stage transistors (141, 142, 143, 144) resulting in faster switching times by reducing input stage offset and, hence improving input dynamic range.

Abstract: The present invention comprises a pair of circuits (171, 172) within the first stage (100) of an AC signal pre-amplifier. The present invention reduces the current mismatch at the base of the first stage transistors (141, 142, 143, 144) resulting in faster switching times by reducing input stage offset and, hence improving input dynamic range.

Abstract: A system for providing feedback to a selected read head in a multi-head disk drive includes first and second feedback circuits is disclosed. A first feedback circuit 200 provides for correction of the output of the selected read head during normal operation. The first feedback circuit 200 produces a differential output current proportional to an offset voltage detected on the read head output nodes 103 and 104. This differential output current charges external capacitor 190. The voltage across capacitor 190 is supplied to voltage inputs of the selected read head as a feedback voltage. When the feedback voltage reaches the desired level, nodes 103 and is 104 equalize, as do the output currents of the first feedback circuit 200. The second feedback circuit 300 provides for quick recovery of the system after a change in read heads.

Abstract: The open condition detection circuit (10) detects breakage in an external write magnetic coil (16, 18) in a hard disk drive. The magnetic coil (16, 18) receives write head signals H.sub.X and H.sub.Y generated by a write driver (12, 14) in response to write data D.sub.X and D.sub.Y. The circuit (10) includes a comparator (26, 28) coupled to the write driver (12, 14) for comparing both the write head signals H.sub.X and H.sub.Y with a predetermined reference voltage level and generating first and second differential comparison output signals. A first latch (40, 150) is coupled to the comparator (26, 28) and uses the write data D.sub.X and D.sub.Y as clock signals for latching the first differential comparison output signal just prior to a predetermined polarity change in the write head signal H.sub.X. A second latch (42, 154) is also coupled to the comparator (26, 28) and is clocked by the write data D.sub.X and D.sub.