Patents by Inventor Hisao Shigekane

Hisao Shigekane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6242967
    Abstract: A semiconductor device is provided which includes a first unipolar transistor provided in a front stage of the device, second unipolar transistor provided in the front stage, and a bipolar transistor provided in a rear stage of the device. In this semiconductor device, drain and the source of the first unipolar transistor are connected to collector and the base of the bipolar transistor, respectively, and drain and the source of the second unipolar transistor are connected to emitter and base of the bipolar transistor, respectively.
    Type: Grant
    Filed: June 15, 1999
    Date of Patent: June 5, 2001
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Noriyuji Iwamuro, Hisao Shigekane, Yuichi Harada, Tadayoshi Iwaana
  • Patent number: 5469103
    Abstract: A semiconductor device, comprising a transistor, a constant voltage diode having a first end of a first conductivity type connected to an emitter of the transistor and a second end of a second conductivity type, a reverse current preventive diode having a first end of the first conductivity type connected to a collector of the transistor and a second end of the second conductivity type connected to the second end of the constant voltage diode, and a high speed diode reverse-bias connected between the transistor collector and the emitter of the transistor.
    Type: Grant
    Filed: March 22, 1994
    Date of Patent: November 21, 1995
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Hisao Shigekane
  • Patent number: 5349230
    Abstract: A semiconductor device, comprising a transistor, a constant voltage diode having a first end of a first conductivity type connected to an emitter of the transistor and a second end of a second conductivity type, a reverse current preventive diode having a first end of the first conductivity type connected to a collector of the transistor and a second end of the second conductivity type connected to the second end of the constant voltage diode, and a high speed diode reverse-bias connected between the transistor collector and the emitter of the transistor.
    Type: Grant
    Filed: October 28, 1991
    Date of Patent: September 20, 1994
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Hisao Shigekane
  • Patent number: 5115388
    Abstract: In an inverter which converts a DC voltage input into AC voltage outputs of different phases, power transistors are arranged in an upper arm and a lower arm of the inverter. The temperatures of the power transistors in the upper arm are monitored by individual temperature sensors connected to overheat protection circuits. When an overcurrent flows through any one of the power transistors in the upper arm in a short-circuit situation, that power transistor is overheated. An alarm signal is initiated by the corresponding overheat protection circuit once the temperature of the power transistor is sensed to have exceeded a predetermined value. In response to this alarm signal, all of the power transistors are turned off and, thus, accorded protection.
    Type: Grant
    Filed: February 26, 1991
    Date of Patent: May 19, 1992
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Hisao Shigekane
  • Patent number: 4945396
    Abstract: A semiconductor device, CHARACTERIZED in that a Darlington transistor in which in one surface of a semiconductor of a first conductivity type, base regions of a second conductivity type, the number of which is larger that the number of base-emitter junctions of the transistor, are formed, emitter regions of the first conductivity type are formed in the base regions, respectively, and base electrodes and emitter electrodes are connected to the base regions and emitter regions, respectively, and are further connected in such a manner that the base electrode of a base region is connected to the emitter electrode in the next base region, is the same in conductivity type arrangement as the transistor and is mounted on the same substrate as the transistor in such a manner that the Darlington transistor is insulated from the transistor, and the base electrode of the transistor is connected to the collector electrode of the Darlington transistor which is formed on the other surface of the semiconductor and to the bas
    Type: Grant
    Filed: December 15, 1989
    Date of Patent: July 31, 1990
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Hisao Shigekane, Shinichi Ito
  • Patent number: 4920405
    Abstract: An overcurrent limiting semiconductor device is provided comprising: a package having a base plate, sidewalls and a cover plate, at least one transistor fixed onto the base plate, terminal conductors respectively connected to the base, emitter and collector electrodes of the transistor which are led out through the cover plate, and a plurality of diode connected in series across the base/emitter of the transistor, with the diodes being disposed in a space provided between the cover plate and the base plate of the package, and connected to the base and emitter terminal conductors. This construction provides an integral overcurrent limiting semiconductor device which minimizes unnecessary limiting of the transistor collector-emitter current caused by a heating of the diodes by the transistor.
    Type: Grant
    Filed: November 25, 1987
    Date of Patent: April 24, 1990
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Shinichi Itoh, Hisao Shigekane
  • Patent number: 4905069
    Abstract: In the particular embodiment described in the specification, a Darlington transistor arrangement has a stepped upper surface with an emitter terminal of the preceding transistor disposed at the bottom of a groove formed between spaced raised portions on which the collector terminal and the emitter terminal of the transistor are located. A base terminal is disposed at a lower surface formed on the outside of the raised portion where either the collector terminal or the emitter terminal is situated, thereby providing sufficient insulation distance between terminals and avoiding the problem resulting from a crossing between the power wiring to the load or power source and the base driving wiring.
    Type: Grant
    Filed: November 13, 1984
    Date of Patent: February 27, 1990
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Hisao Shigekane
  • Patent number: 4782378
    Abstract: A resistively stabilized transistor in which secondary breakdown is prevented by the insertion of a floating emitter protection region around only one end of a stabilizing resistive region. The transistor includes an ordinary emitter region located within a base region. A floating emitter region surrounds the ordinary emitter region. An elongated stabilizing resistive region has one end connected to the ordinary emitter region and the other to the base region. The protection region is positioned around, but spaced from, an end portion of the stabilizing resistive region only in the area where the resistive region connects to the ordinary emitter region.
    Type: Grant
    Filed: November 18, 1987
    Date of Patent: November 1, 1988
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Tsuneto Sekiya, Shinichi Ito, Hisao Shigekane
  • Patent number: 4746814
    Abstract: A semiconductor device comprising first and second transistors connected in series with one another to pass a primary current upon receipt of a control signal at the gate of the second transistor. The first transistor is coupled to receive a base current from a secondary power source. A third transistor is coupled to have a current path shunt that base current away from the first transistor upon conduction of the third transistor. A control electrode of the third transistor is coupled to receive the control signal also received at the gate of the second transistor. The polarity of the third transistor is selected to render the third transistor conductive when the second transistor is rendered non-conductive in response to the control signal and to render the third transistor non-conductive when the second transistor is rendered conductive by the control signal.
    Type: Grant
    Filed: June 17, 1986
    Date of Patent: May 24, 1988
    Assignee: Fuji Electric Company Ltd.
    Inventor: Hisao Shigekane
  • Patent number: 4739199
    Abstract: A semiconductor device comprising first and second transistors connected in series with one another to pass a primary current upon receipt of a control signal at the gate of the second transistor. The first transistor is coupled to receive a base current from a secondary power source. A third transistor is coupled to have a primary current path to shunt the base current away from the first transistor upon conduction of the third transistor. A capacitor is connected between the base of the third transistor and the base of the first transistor so that, at the moment the second transistor ceases conduction in response to the control signal, a voltage gradient is generated between the base of the first transistor and the base of the third transistor, causing the current from the secondary power source to charge the capacitor and thus render the third transistor conductive, thereby shunting the base current from the secondary power source away from the base of the first transistor.
    Type: Grant
    Filed: June 18, 1986
    Date of Patent: April 19, 1988
    Assignee: Fuji Electric Company Ltd.
    Inventor: Hisao Shigekane
  • Patent number: 4717849
    Abstract: A semiconductor device comprising first and second transistors connected in series with one another to provide a path for a primary current upon receipt of a control signal at the gate of the second transistor. The first transistor is coupled to receive a base current from a secondary power source. A third transistor is coupled to have a current path which shunts the base current of the first transistor upon conduction of the third transistor. A zener diode is connected between the base of the third transistor and the common junction of the first and second transistors and is arranged to provide base current to the third transistor thereby causing the third transistor to be conductive upon turn-OFF of the second transistor, and as a consequence quickly turning OFF the first transistor.
    Type: Grant
    Filed: June 17, 1986
    Date of Patent: January 5, 1988
    Assignee: Fuji Electric Company Ltd.
    Inventor: Hisao Shigekane
  • Patent number: 4651035
    Abstract: A switching circuit which uses a compound transistor pair as the switch employs to improve the switching properties a circuit branch which comprises an auxiliary transistor and a zener diode. In a preferred embodiment, the branch also included a voltage-divider resistor network to control the maximum current through the switch.
    Type: Grant
    Filed: October 9, 1985
    Date of Patent: March 17, 1987
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Hisao Shigekane