Patents by Inventor Hisao Shigematsu

Hisao Shigematsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10651305
    Abstract: A compound semiconductor device includes a substrate, a compound semiconductor layer formed over the substrate, a channel layer formed over the compound semiconductor layer, an electron supply layer formed over the channel layer, and a source electrode, a drain electrode, and a gate electrode that are formed apart from each other over the electron supply layer. A quantum well structure is formed by the compound semiconductor layer, the channel layer, and the electron supply layer.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: May 12, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Junji Kotani, Norikazu Nakamura, Hisao Shigematsu
  • Publication number: 20190043976
    Abstract: A compound semiconductor device includes a substrate, a compound semiconductor layer formed over the substrate, a channel layer formed over the compound semiconductor layer, an electron supply layer formed over the channel layer, and a source electrode, a drain electrode, and a gate electrode that are formed apart from each other over the electron supply layer. A quantum well structure is formed by the compound semiconductor layer, the channel layer, and the electron supply layer.
    Type: Application
    Filed: July 26, 2018
    Publication date: February 7, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Junji Kotani, Norikazu Nakamura, Hisao Shigematsu
  • Patent number: 7928815
    Abstract: An amplifier according to the present invention includes an amplifying transistor, and an impedance converter circuit coupled to an output unit of the amplifying transistor and including a plurality of impedance converting transistors different in input impedance, which are series-connected.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: April 19, 2011
    Assignee: Fujitsu Limited
    Inventor: Hisao Shigematsu
  • Patent number: 7804357
    Abstract: In order to allow to make compact a distributed amplifier by dispensing with any choke coil and reduce its cost, the distributed amplifier is configured such that it comprises an input side transmission line, an output side transmission line, and plural amplifier circuits connected to the input side transmission line and the output side transmission line, wherein push-pull amplifier circuits are employed as the amplifier circuits.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: September 28, 2010
    Assignee: Fujitsu Limited
    Inventor: Hisao Shigematsu
  • Patent number: 7782140
    Abstract: A resistor (9-1) and a resistor (11-1) are connected in parallel with each other between a source of an input transistor (7-1) and the ground. A switch (12-1) is provided between the resistor (11-1) and the source. A variable resistor circuit may be constituted by the resistor (9-1), the resistor (11-1) and the switch (12-1). Further, a capacitor (10-1) and a variable capacitor (13-1) are connected in series with each other between the source and the ground. A control terminal (14-1) to which a voltage is applied when capacitance of the variable capacitor (13-1) is controlled is provided between the capacitor (10-1) and the variable capacitor (13-1). A variable capacitor circuit may be constituted by the capacitor (10-1) and the variable capacitor (13-1). An input capacitance change circuit may be constituted by the variable resistor circuit and the variable capacitor circuit.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: August 24, 2010
    Assignee: Fujitsu Limited
    Inventor: Hisao Shigematsu
  • Publication number: 20090009253
    Abstract: A resistor (9-1) and a resistor (11-1) are connected in parallel with each other between a source of an input transistor (7-1) and the ground. A switch (12-1) is provided between the resistor (11-1) and the source. A variable resistor circuit may be constituted by the resistor (9-1), the resistor (11-1) and the switch (12-1). Further, a capacitor (10-1) and a variable capacitor (13-1) are connected in series with each other between the source and the ground. A control terminal (14-1) to which a voltage is applied when capacitance of the variable capacitor (13-1) is controlled is provided between the capacitor (10-1) and the variable capacitor (13-1). A variable capacitor circuit may be constituted by the capacitor (10-1) and the variable capacitor (13-1). An input capacitance change circuit may be constituted by the variable resistor circuit and the variable capacitor circuit.
    Type: Application
    Filed: September 19, 2008
    Publication date: January 8, 2009
    Applicant: FUJITSU LIMITED
    Inventor: Hisao SHIGEMATSU
  • Publication number: 20080231367
    Abstract: An amplifier according to the present invention includes an amplifying transistor, and an impedance converter circuit coupled to an output unit of the amplifying transistor and including a plurality of impedance converting transistors different in input impedance, which are series-connected.
    Type: Application
    Filed: March 13, 2008
    Publication date: September 25, 2008
    Applicant: Fujitsu Limited
    Inventor: Hisao SHIGEMATSU
  • Patent number: 7323947
    Abstract: An oscillator circuit includes first and second transistors forming a differential pair, an output combiner connected to first terminal sides of the first and second transistors, and a current source connected to second terminal sides of the first and second transistors.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: January 29, 2008
    Assignee: Fujitsu Limited
    Inventor: Hisao Shigematsu
  • Publication number: 20060284213
    Abstract: The semiconductor device comprises a collector layer 14; a base layer 16 of a carbon-doped GaxIn1-xAsySb1-y layer having one surface connected to the collector layer 14; an emitter layer 18 connected the other surface of the base layer 16; a base contact layer 30 of a carbon-doped GaAsSb layer electrically connected to the base layer 16; and a base electrode 32 formed on the base contact layer 30. The semiconductor device of such structure can have a much reduced base resistance RB, whereby InP/GaInAsSb-based HBTs including InP/InGaAs-based HBTs can have higher maximum oscillation frequency fmax. Because of the carbon-doped semiconductor layer the semiconductor device can have higher reliability.
    Type: Application
    Filed: August 23, 2006
    Publication date: December 21, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Hisao Shigematsu, Kenji Imanishi, Hitoshi Tanaka
  • Publication number: 20060279360
    Abstract: In order to allow to make compact a distributed amplifier by dispensing with any choke coil and reduce its cost, the distributed amplifier is configured such that it comprises an input side transmission line, an output side transmission line, and plural amplifier circuits connected to the input side transmission line and the output side transmission line, wherein push-pull amplifier circuits are employed as the amplifier circuits.
    Type: Application
    Filed: September 29, 2005
    Publication date: December 14, 2006
    Inventor: Hisao Shigematsu
  • Publication number: 20060033590
    Abstract: An oscillator circuit includes first and second transistors forming a differential pair, an output combiner connected to first terminal sides of the first and second transistors, and a current source connected to second terminal sides of the first and second transistors.
    Type: Application
    Filed: December 29, 2004
    Publication date: February 16, 2006
    Inventor: Hisao Shigematsu
  • Patent number: 6930557
    Abstract: A multi-stage amplifier includes first and second amplifier stages, and first and second capacitors. The first amplifier stage includes a input line having a first input end and a second input end; an input terminal block connected to the second input end; an amplifier circuit amplifying a first signal input to the first input end; an output line having a first output end where the first signal amplified is output, and a second output end; and an output terminal block connected to the second output end. The second amplifier stage includes components similar to that of the first amplifier stage. The first capacitor is connected between the first output end of the first amplifier stage and the first input end of the second amplifier stage. The second capacitor is connected to any one of the input and output terminal blocks of the first and second amplifier stages.
    Type: Grant
    Filed: October 24, 2003
    Date of Patent: August 16, 2005
    Assignee: Fujitsu Limited
    Inventor: Hisao Shigematsu
  • Patent number: 6864750
    Abstract: In a cascode distributed amplifier of the present invention, a plurality of unit circuits are connected in parallel, and each unit circuit includes a pair of first and second transistors connected in series between an input transmission wire and an output transmission wire. The first transistor has a gate connected to the input transmission wire, a source grounded and a drain connected to the second transistor. The second transistor has a gate grounded, a source connected to the drain of the first transistor and a drain connected to the output transmission wire. Each unit circuit includes a damping resistor having a first end connected to the gate of the second transistor and a second end, and a capacitor having a first end connected to the second end of the damping resistor and a second end grounded.
    Type: Grant
    Filed: March 14, 2002
    Date of Patent: March 8, 2005
    Assignee: Fujitsu Limited
    Inventor: Hisao Shigematsu
  • Publication number: 20040085133
    Abstract: A multi-stage amplifier includes first and second amplifier stages, and first and second capacitors. The first amplifier stage includes a input line having a first input end and a second input end; an input terminal block connected to the second input end; an amplifier circuit amplifying a first signal input to the first input end; an output line having a first output end where the first signal amplified is output, and a second output end; and an output terminal block connected to the second output end. The second amplifier stage includes components similar to that of the first amplifier stage. The first capacitor is connected between the first output end of the first amplifier stage and the first input end of the second amplifier stage. The second capacitor is connected to any one of the input and output terminal blocks of the first and second amplifier stages.
    Type: Application
    Filed: October 24, 2003
    Publication date: May 6, 2004
    Applicant: FUJITSU LIMITED
    Inventor: Hisao Shigematsu
  • Publication number: 20030011436
    Abstract: In a cascode distributed amplifier of the present invention, a plurality of unit circuits are connected in parallel, and each unit circuit includes a pair of first and second transistors connected in series between an input transmission wire and an output transmission wire. The first transistor has a gate connected to the input transmission wire, a source grounded and a drain connected to the second transistor. The second transistor has a gate grounded, a source connected to the drain of the first transistor and a drain connected to the output transmission wire. Each unit circuit includes a damping resistor having a first end connected to the gate of the second transistor and a second end, and a capacitor having a first end connected to the second end of the damping resistor and a second end grounded.
    Type: Application
    Filed: March 14, 2002
    Publication date: January 16, 2003
    Applicant: FUJITSU LIMITED
    Inventor: Hisao Shigematsu
  • Patent number: 6472941
    Abstract: A plurality of amplifying circuits 31 to 34 are connected between input and output transmission circuits 10 and 20 in a forward direction, a bias-T 29 is connected to an output terminal OUT of the transmission circuit 20, and a DC bias voltage VDD1 is applied to the outputs of the amplifying circuits 31 to 34 through the inductor 292 of the circuit 29 and the transmission circuit 20. The opposite end to the output terminal OUT is grounded through a series connection of a terminating resistor R2 and a DC voltage source 30 having an output voltage VDD 2. Since VDD1=VDD1, the DC voltage across the terminating resistor R2 is zero. The inductor 292 may be connected in parallel to the terminating resistor R2 with omitting the bias voltage VDD1.
    Type: Grant
    Filed: April 5, 2001
    Date of Patent: October 29, 2002
    Assignee: Fujitsu Limited
    Inventor: Hisao Shigematsu
  • Publication number: 20020090789
    Abstract: The semiconductor device comprises a collector layer 14; a base layer 16 of a carbon-doped GaxIn1−xAsySb1−y layer having one surface connected to the collector layer 14; an emitter layer 18 connected the other surface of the base layer 16; a base contact layer 30 of a carbon-doped GaAsSb layer electrically connected to the base layer 16; and a base electrode 32 formed on the base contact layer 30. The semiconductor device of such structure can have a much reduced base resistance RB, whereby InP/GaInAsSb-based HBTs including InP/InGaAs-based HBTs can have higher maximum oscillation frequency fmax. Because of the carbon-doped semiconductor layer the semiconductor device can have higher reliability.
    Type: Application
    Filed: March 8, 2002
    Publication date: July 11, 2002
    Applicant: FUJITSU LIMITED
    Inventors: Hisao Shigematsu, Kenji Imanishi, Hitoshi Tanaka
  • Patent number: 6399971
    Abstract: The semiconductor device comprises a collector layer 14; a base layer 16 of a carbon-doped GaxIn1−xAsySb1−y layer having one surface connected to the collector layer 14; an emitter layer 18 connected the other surface of the base layer 16; a base contact layer 30 of a carbon-doped GaAsSb layer electrically connected to the base layer 16; and a base electrode 32 formed on the base contact layer 30. The semiconductor device of such structure can have a much reduced base resistance RB, whereby InP/GaInAsSb-based HBTs including InP/InGaAs-based HBTs can have higher maximum oscillation frequency fmax. Because of the carbon-doped semiconductor layer the semiconductor device can have higher reliability.
    Type: Grant
    Filed: November 13, 1998
    Date of Patent: June 4, 2002
    Assignee: Fujitsu Limited
    Inventors: Hisao Shigematsu, Kenji Imanishi, Hitoshi Tanaka
  • Publication number: 20020027232
    Abstract: The semiconductor device comprises a collector layer 14; a base layer 16 of a carbon-doped GaxIn1-xAsySb1-y layer having one surface connected to the collector layer 14; an emitter layer 18 connected the other surface of the base layer 16; a base contact layer 30 of a carbon-doped GaAsSb layer electrically connected to the base layer 16; and a base electrode 32 formed on the base contact layer 30. The semiconductor device of such structure can have a much reduced base resistance RB, whereby InP/GaInAsSb-based HBTs including InP/InGaAs-based HBTs can have higher maximum oscillation frequency fmax. Because of the carbon-doped semiconductor layer the semiconductor device can have higher reliability.
    Type: Application
    Filed: November 13, 1998
    Publication date: March 7, 2002
    Inventors: HISAO SHIGEMATSU, KENJI IMANISHI, HITOSHI TANAKA
  • Publication number: 20020008583
    Abstract: A plurality of amplifying circuits 31 to 34 are connected between input and output transmission circuits 10 and 20 in a forward direction, a bias-T 29 is connected to an output terminal OUT of the transmission circuit 20, and a DC bias voltage VDD1 is applied to the outputs of the amplifying circuits 31 to 34 through the inductor 292 of the circuit 29 and the transmission circuit 20. The opposite end to the output terminal OUT is grounded through a series connection of a terminating resistor R2 and a DC voltage source 30 having an output voltage VDD 2. Since VDD1=VDD1, the DC voltage across the terminating resistor R2 is zero. The inductor 292 may be connected in parallel to the terminating resistor R2 with omitting the bias voltage VDD1.
    Type: Application
    Filed: April 5, 2001
    Publication date: January 24, 2002
    Applicant: Fujitsu Limited
    Inventor: Hisao Shigematsu