Patents by Inventor Hisao Sudo

Hisao Sudo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8802468
    Abstract: A semiconductor light emitting device includes a lower cladding layer, an active layer, and an AlGaAs upper cladding layer mounted on a GaAs substrate. The semiconductor light emitting device has a ridge structure including the AlGaAs upper cladding layer. The semiconductor light emitting device further includes an InGaAs etching stop layer provided in contact with the lower side of the AlGaAs upper cladding layer. The InGaAs etching stop layer has a band gap greater than that of the active layer.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: August 12, 2014
    Assignees: Fujitsu Limited, The University of Tokyo
    Inventors: Nobuaki Hatori, Tsuyoshi Yamamoto, Hisao Sudo, Yasuhiko Arakawa
  • Patent number: 8716044
    Abstract: A p-type cladding layer (3) of p-type semiconductor is formed over a substrate. An active layer (5) including a p-type semiconductor region is disposed over the p-type cladding layer. A buffer layer (10) of non-doped semiconductor is disposed over the active layer. A ridge-shaped n-type cladding layer (11) of n-type semiconductor is disposed over a partial surface of the buffer layer. The buffer layer on both sides of the ridge-shaped n-type cladding layer is thinner than the buffer layer just under the ridge-shaped n-type cladding layer.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: May 6, 2014
    Assignee: Fujitsu Limited
    Inventors: Tsuyoshi Yamamoto, Hisao Sudo
  • Publication number: 20140017841
    Abstract: A p-type cladding layer (3) of p-type semiconductor is formed over a substrate. An active layer (5) including a p-type semiconductor region is disposed over the p-type cladding layer. A buffer layer (10) of non-doped semiconductor is disposed over the active layer. A ridge-shaped n-type cladding layer (11) of n-type semiconductor is disposed over a partial surface of the buffer layer. The buffer layer on both sides of the ridge-shaped n-type cladding layer is thinner than the buffer layer just under the ridge-shaped n-type cladding layer.
    Type: Application
    Filed: September 16, 2013
    Publication date: January 16, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Tsuyoshi YAMAMOTO, Hisao SUDO
  • Patent number: 8558245
    Abstract: A p-type cladding layer (3) of p-type semiconductor is formed over a substrate. An active layer (5) including a p-type semiconductor region is disposed over the p-type cladding layer. A buffer layer (10) of non-doped semiconductor is disposed over the active layer. A ridge-shaped n-type cladding layer (11) of n-type semiconductor is disposed over a partial surface of the buffer layer. The buffer layer on both sides of the ridge-shaped n-type cladding layer is thinner than the buffer layer just under the ridge-shaped n-type cladding layer.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: October 15, 2013
    Assignee: Fujitsu Limited
    Inventors: Tsuyoshi Yamamoto, Hisao Sudo
  • Publication number: 20130267054
    Abstract: A semiconductor light emitting device includes a lower cladding layer, an active layer, and an AlGaAs upper cladding layer mounted on a GaAs substrate. The semiconductor light emitting device has a ridge structure including the AlGaAs upper cladding layer. The semiconductor light emitting device further includes an InGaAs etching stop layer provided in contact with the lower side of the AlGaAs upper cladding layer. The InGaAs etching stop layer has a band gap greater than that of the active layer.
    Type: Application
    Filed: June 5, 2013
    Publication date: October 10, 2013
    Inventors: Nobuaki Hatori, Tsuyoshi Yamamoto, Hisao Sudo, Yasuhiko Arakawa
  • Patent number: 8483252
    Abstract: A semiconductor light emitting device includes a lower cladding layer, an active layer, and an AlGaAs upper cladding layer mounted on a GaAs substrate. The semiconductor light emitting device has a ridge structure including the AlGaAs upper cladding layer. The semiconductor light emitting device further includes an InGaAs etching stop layer provided in contact with the lower side of the AlGaAs upper cladding layer. The InGaAs etching stop layer has a band gap greater than that of the active layer.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: July 9, 2013
    Assignees: Fujitsu Limited, The University of Tokyo
    Inventors: Nobuaki Hatori, Tsuyoshi Yamamoto, Hisao Sudo, Yasuhiko Arakawa
  • Patent number: 8232125
    Abstract: An active layer having a p-type quantum dot structure is disposed over a lower cladding layer made of semiconductor material of a first conductivity type. An upper cladding layer is disposed over the active layer. The upper cladding layer is made of semiconductor material, and includes a ridge portion and a cover portion. The ridge portion extends in one direction, and the cover portion covers the surface on both sides of the ridge portion. A capacitance reducing region is disposed on both sides of the ridge portion and reaching at least the lower surface of the cover portion. The capacitance reducing region has the first conductivity type or a higher resistivity than that of the ridge portion, and the ridge portion has a second conductivity type. If the lower cladding layer is an n-type, the capacitance reducing region reaches at least the upper surface of the lower cladding layer.
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: July 31, 2012
    Assignees: Fujitsu Limited, The University of Tokyo
    Inventors: Nobuaki Hatori, Tsuyoshi Yamamoto, Hisao Sudo, Yasuhiko Arakawa
  • Publication number: 20090263926
    Abstract: An active layer having a p-type quantum dot structure is disposed over a lower cladding layer made of semiconductor material of a first conductivity type. An upper cladding layer is disposed over the active layer. The upper cladding layer is made of semiconductor material, and includes a ridge portion and a cover portion. The ridge portion extends in one direction, and the cover portion covers the surface on both sides of the ridge portion. A capacitance reducing region is disposed on both sides of the ridge portion and reaching at least the lower surface of the cover portion. The capacitance reducing region has the first conductivity type or a higher resistivity than that of the ridge portion, and the ridge portion has a second conductivity type. If the lower cladding layer is an n-type, the capacitance reducing region reaches at least the upper surface of the lower cladding layer.
    Type: Application
    Filed: June 18, 2009
    Publication date: October 22, 2009
    Applicants: FUJITSU LIMITED, THE UNIVERSITY OF TOKYO
    Inventors: Nobuaki Hatori, Tsuyoshi Yamamoto, Hisao Sudo, Yasuhiko Arakawa
  • Patent number: 7573060
    Abstract: An active layer having a p-type quantum dot structure is disposed over a lower cladding layer made of semiconductor material of a first conductivity type. An upper cladding layer is disposed over the active layer. The upper cladding layer is made of semiconductor material, and includes a ridge portion and a cover portion. The ridge portion extends in one direction, and the cover portion covers the surface on both sides of the ridge portion. A capacitance reducing region is disposed on both sides of the ridge portion and reaching at least the lower surface of the cover portion. The capacitance reducing region has the first conductivity type or a higher resistivity than that of the ridge portion, and the ridge portion has a second conductivity type. If the lower cladding layer is an n-type, the capacitance reducing region reaches at least the upper surface of the lower cladding layer.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: August 11, 2009
    Assignees: Fujitsu Limited, The University of Tokyo
    Inventors: Nobuaki Hatori, Tsuyoshi Yamamoto, Hisao Sudo, Yasuhiko Arakawa
  • Publication number: 20080232417
    Abstract: A semiconductor light emitting device includes a lower cladding layer, an active layer, and an AlGaAs upper cladding layer mounted on a GaAs substrate. The semiconductor light emitting device has a ridge structure including the AlGaAs upper cladding layer. The semiconductor light emitting device further includes an InGaAs etching stop layer provided in contact with the lower side of the AlGaAs upper cladding layer. The InGaAs etching stop layer has a band gap greater than that of the active layer.
    Type: Application
    Filed: March 19, 2008
    Publication date: September 25, 2008
    Applicants: FUJITSU LIMITED, THE UNIVERSITY OF TOKYO
    Inventors: Nobuaki HATORI, Tsuyoshi YAMAMOTO, Hisao SUDO, Yasuhiko ARAKAWA
  • Publication number: 20080197377
    Abstract: A photonic semiconductor device which includes a semiconductor layer having a ridge-form protruding part formed on a semiconductor substrate. A resin layer is formed on surface parts on both sides of the protruding part so that the protruding part is embedded, and a first insulating film includes an opening that is formed on the resin layer which exposes an upper surface of the protruding part and a portion of a upper surface of the resin layer on both sides of the protruding part. A first electrode is formed in the opening so as to cover the upper surface of the protruding part, and electrically couple to an upper part of the protruding part; and a second electrode, which electrically couples to the first electrode, is formed on the first electrode and the first insulation film.
    Type: Application
    Filed: February 15, 2008
    Publication date: August 21, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Hisao SUDO, Tsuyoshi YAMAMOTO
  • Publication number: 20080157059
    Abstract: An active layer having a p-type quantum dot structure is disposed over a lower cladding layer made of semiconductor material of a first conductivity type. An upper cladding layer is disposed over the active layer. The upper cladding layer is made of semiconductor material, and includes a ridge portion and a cover portion. The ridge portion extends in one direction, and the cover portion covers the surface on both sides of the ridge portion. A capacitance reducing region is disposed on both sides of the ridge portion and reaching at least the lower surface of the cover portion. The capacitance reducing region has the first conductivity type or a higher resistivity than that of the ridge portion, and the ridge portion has a second conductivity type. If the lower cladding layer is an n-type, the capacitance reducing region reaches at least the upper surface of the lower cladding layer.
    Type: Application
    Filed: October 22, 2007
    Publication date: July 3, 2008
    Applicants: FUJITSU LIMITED, THE UNIVERSITY OF TOKYO
    Inventors: Nobuaki Hatori, Tsuyoshi Yamamoto, Hisao Sudo, Yasuhiko Arakawa
  • Publication number: 20080073716
    Abstract: A p-type cladding layer (3) of p-type semiconductor is formed over a substrate. An active layer (5) including a p-type semiconductor region is disposed over the p-type cladding layer. A buffer layer (10) of non-doped semiconductor is disposed over the active layer. A ridge-shaped n-type cladding layer (11) of n-type semiconductor is disposed over a partial surface of the buffer layer. The buffer layer on both sides of the ridge-shaped n-type cladding layer is thinner than the buffer layer just under the ridge-shaped n-type cladding layer.
    Type: Application
    Filed: January 19, 2007
    Publication date: March 27, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Tsuyoshi Yamamoto, Hisao Sudo