Patents by Inventor Hisao Tosaka

Hisao Tosaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Dry etching method of silicon compound film
    Patent number: 8394686
    Abstract: A silicon compound film is dry etched by parallel-plate type dry etching using an etching gas including at least COF2.
    Type: Grant
    Filed: September 8, 2009
    Date of Patent: March 12, 2013
    Assignee: Casio Computer Co., Ltd.
    Inventor: Hisao Tosaka
  • DRY ETCHING METHOD OF SILICON COMPOUND FILM
    Publication number: 20100075491
    Abstract: A silicon compound film is dry etched by parallel-plate type dry etching using an etching gas including at least COF2.
    Type: Application
    Filed: September 8, 2009
    Publication date: March 25, 2010
    Applicant: Casio Computer Co., Ltd.
    Inventor: Hisao TOSAKA
  • Silicon nitride film dry etching method
    Publication number: 20080299777
    Abstract: A silicon nitride film is dry etched by reactive ion etching using a mixed gas including a fluorine gas and an oxygen gas.
    Type: Application
    Filed: May 28, 2008
    Publication date: December 4, 2008
    Applicant: Casio Computer Co.,Ltd.
    Inventor: Hisao Tosaka
  • Silicon film dry etching method
    Publication number: 20080299778
    Abstract: A silicon film is dry etched by parallel plate type dry etching using a mixed gas including a fluorine gas and a chlorine gas.
    Type: Application
    Filed: May 28, 2008
    Publication date: December 4, 2008
    Applicant: Casio Computer Co., Ltd.
    Inventor: Hisao Tosaka
  • Method of manufacturing transistor array
    Patent number: 6069019
    Abstract: According to the present invention, a gate insulation film, a silicon film and silicon nitride film are laminated on a gate backing pad made of a gate metal film, and etching is carried out on the silicon nitride film such that it remains on the gate backing pad as a protective insulation film. Thus, the corrosion of the gate backing pad, which is caused as the etching solution penetrate the silicon film in defect, can be prevented. Further, a protective semiconductor layer formed by patterning the protective insulation film and the silicon film, is formed above the gate backing pad. Thus, the gate backing pad can be protected from the etching solution during the patterning of the pixel electrode made of ITO. Therefore, the disconnection of the gate backing pad can be prevented.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: May 30, 2000
    Assignee: Casio Computer Co., Ltd.
    Inventors: Hiromitsu Ishii, Hisao Tosaka