Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRUM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.

Abstract: Serial write data of the burst length transmitted to a data bus are stored in parallel in latch circuits by a S/P data conversion circuit. In a memory cell array, one row of memory cells and four columns of memory cells are rendered active at the same time. Respective bit lines and latch circuits are connected by a sense amplifier I/O circuit. The write data of the burst length are written into the memory cell array at one time. The data of the bit length read out at one time from the memory cell array are converted into serial data by a P/S data conversion circuit to be transmitted to the data bus.

Abstract: An internal clock signal generating circuit includes a selector, a delay line, a 2-frequency divider, a phase comparator and a shift register. The selector alternately selects an external clock signal and an internal clock signal output from the delay line and outputs the selected signal to the delay line. The delay line receiving the signal delays the external clock signal, and delays the internal clock signal output from itself. The 2-frequency divider divides frequency of the internal clock signal by 2. Phase comparator compares phases of the external clock signal and the output signal from the 2-frequency divider. Delay time of the delay line is adjusted by the phase comparator and the shift register so that the phase difference is made 0.

Abstract: An input buffer of a semiconductor device is provided. A first voltage shift circuit converts an input signal formed of a low amplitude logic signal overlapping 1.65V or 2.9V to a first signal formed of a complimentary signal formed of the low amplitude logic signal overlapping 2.9V or 1.65V. A second voltage shift circuit converts a reference potential of 1.65V or 2.9V to a second signal of 2.9V or 1.65V. A differential amplifier compares the reference potential with the input signal when the reference potential is 1.65V, and compares the first signal and the second signal when the reference potential is 2.9V. The input buffer thus operates normally whichever of 1.65V and 2.9V is the reference potential.

Abstract: A semiconductor memory device is configured to include a static random access memory (SRAM) array and a dynamic random access memory (DRAM) array. The memory device includes an internal data line which enables the transfer of data blocks between the SRAM and DRAM arrays. Data transfer circuitry is provided separately from the internal data line and includes a latch circuit for latching the data to be transferred. The data transfer circuitry is responsive to a transfer designating signal.

Abstract: A synchronous semiconductor memory device includes a prefetch selector receiving first and second data respectively read from first and second memory cells corresponding to even and odd addresses for outputting them to a data input/output terminal. The prefetch selector sequentially outputs first and second data to the data input/output terminal in one period of a clock period in the normal operation, determines if the first and second data match in a test mode, and outputs the determination result to the data input/output terminal in one period of the clock period.

Abstract: A synchronous semiconductor memory device capable of improving substantial transfer rate is provided. In response to a write command immediately following an act command, a control signal generating circuit applies an inactive enable signal to a read preamplifier & write buffer. In response to a write command and a precharge command, the control signal generating circuit generates an active enable signal, and the read preamplifier & write buffer writes the data stored in an FIFO to a memory cell. As late write is not performed upon reception of a write command immediately following an act command, erroneous writing of data to a not intended address can be prevented.

Abstract: The phase comparator receives an output of a buffer receiving the first input signal and an output of a buffer receiving the second input signal, and outputs signals SLOW, FAST as a result of phase comparison. The phase comparator includes a waveform processing circuit for enlarging the phase difference between two input signals, and a comparison circuit for performing phase comparison based on the phase difference enlarged by the waveform processing circuit and outputting signals SLOW, FAST. Because of the function of the waveform processing circuit, the performance of the phase comparator can be improved significantly, without having to largely improve the performance of the comparison circuit.

Abstract: An output circuit and a synchronous semiconductor memory device according to the invention suppress output of invalid data, and perform data output with exact timings. The synchronous semiconductor memory device includes a plurality of output buffers provided correspondingly to data I/O terminals, a plurality of data transfer latch circuits and a plurality of output control signal latch circuits. Data transfer latch circuit transfers data read from a memory cell to the corresponding output buffer in response to an internal clock signal. The output control signal latch circuit issues an output control signal to the corresponding output buffer in synchronization with the internal clock signal. Thereby, an output timing of each output buffer can be controlled independently of the other output buffer.

Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.

Abstract: In a synchronous dynamic random access memory (SDRAM), one bank A is divided into banks A0 and A1, and two sets of writing-related circuits are arranged corresponding to each memory cell array bank and are capable of performing writing operation substantially independently. The first and second bits of write data applied successively from the outside world are applied alternately to write registers. Since the I/O line pair is connected to the selected memory cells in respective memory cell array banks after incorporation of the second bit data to be written is completed, the potential levels of the corresponding I/O line pair always change to the corresponding potential levels from the initial state in writing the first and second bit data.

Abstract: An internal clock generation circuit includes a delay line in which a plurality of inverter circuits are connected in series. A switch and a capacitor are connected to an output node of each inverter circuit. The switch connected to each inverter circuit is turned on/off individually according to respective control signals. In response to the switch being turned on, the output node of a corresponding inverter circuit and the capacitor are connected, whereby the capacitance of the output node of the corresponding inverter circuit is altered. As a result, the transmission rate of the signal is altered.

Abstract: One strobe signal (QS) is outputted from a group of two adjacent memory chips (MC(i-1), MCi) in each module. In each group, the second memory chip (MCi) receives a data mask signal (DQM(i-1)) inputted to the adjacent first memory chip (MC(i-1)) as a data mask control signal (DQMCi), and stops outputting the strobe signal (QS) when both the data mask signal (DQMi) for the second memory chip (MCi) and the data mask control signal (DQMCi) are activated. Each memory chip (MCi) receives the data mask signal (DQMi) and stops outputting data. In a synchronous DRAM using a strobe signal as a trigger, this configuration allows reduction in the number of strobe signals.

Abstract: In an internal clock signal generation circuit, a phase comparator for detecting phase difference between an external clock signal and an internal clock signal includes a transistor and a capacitor with respect to a signal line through which a clock signal corresponding to the external clock signal is transmitted, and a transistor and a capacitor with respect to a signal line through which a clock signal corresponding to the internal clock signal is transmitted. The rising timing of the signal having a more lagging phase of the signals of the two signal lines becomes more gentle. As a result, the phase difference is increased, and the phase comparator can compare the phase at high precision.

Abstract: A synchronous semiconductor memory device can achieve either of a pipelined mode and a prefetch mode with one chip. In accordance with CAS (column address strobe) latency 4 instructing signal MCL4 stored in a mode register, a sequence of generation of control signals from a control signal generating circuit is set to either the pipelined mode or the prefetch mode. A mode switching circuit merely switches reset timings of a write buffer in accordance with a CAS latency. Therefore, the internal data write mode can be easily switched in accordance with an operation environment, and the synchronous semiconductor memory device can implement multiple data write modes with one chip.

Abstract: SDRAM 1000 outputs data, in a 2-bit prefetch operation, by simultaneously selecting two columns in memory cell array banks A0 and A1 in accordance with column select signals YE0-YEk and YO0-YOk issued from Y-address operation circuit 68. In a full page mode, data are output from all columns crossing rows alternately selected in memory cell array banks A0 and A1 in accordance with an internal address signal issued from a Y-address counter circuit 82.

Abstract: Memory arrays are divided into banks which can be operated independent from each other. Read data storing registers and write data storing registers operating independent from each other are provided for the banks. The memory array is divided into a plurality of small array blocks, local IO lines are arranged corresponding to each array block, and the local IO lines are connected to global IO lines. The global IO lines are connected to preamplifier groups and to write buffer groups. By control signal generating circuits and by a register control circuit, inhibition of writing of a desired bit only during successive writing operation can be done, data can be collectively written to the selected memory cells when the final data is input if the data writing should be stopped before reaching the wrap length in successive writing, and the timing for activating the memory array when the write cycle should be repeatedly carried out can be delayed.

Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.

Abstract: When an operating frequency is increased and a CAS latency is set longer, a data write end time is delayed by a specific time in response to the change of the CAS latency. The specific time is greater than a period corresponding to the CAS latency. The specific time may be the minimum time necessary for writing second-bit data. The write margin can also be enlarged by delaying the write timing (activation and inactivation) in the interior of a memory itself by one clock cycle of an external clock signal. Thus, a write period for second-bit data is ensured in an SDRAM, even if the operation frequency is increased.

Abstract: Disclosed is a DRAM including a test mode operation capable of testing whether a plurality of memory cells are defective or not in a short time. The DRAM includes a power-on detection signal generator, a power-on reset signal generator, and a test mode instruction signal generator. The power-on detection signal generator detects application of a power supply voltage and generates a power-on detection signal. The power-on reset signal generator is reset by a power-on reset signal, counts at least once an external RAS signal applied after reset and generates a power-on reset signal. The test mode instruction signal generator detects logic states of an internal RAS signal, an internal CAS signal and an internal W signal applied after the power-on reset and generates a test mode instructing signal.