Patents by Inventor Hisashi OWA
Hisashi OWA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230318604Abstract: Provided is a control circuit that controls the amplitude by using a voltage regulator and that has improved accuracy in amplitude control. The control circuit includes a first voltage regulator and a second voltage regulator. The first voltage regulator in the control circuit generates one of a pair of voltages from a predetermined reference voltage and supplies the one of the pair of voltages to one of a power supply terminal and a ground terminal of a driver. In addition, the second voltage regulator generates the other of the pair of voltages from the one of the pair of voltages and supplies the other of the pair of voltages to the other of the power supply terminal and the ground terminal.Type: ApplicationFiled: July 8, 2021Publication date: October 5, 2023Inventors: AKIRA ARAI, HISASHI OWA, TAKASHI NAKAMURA
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Publication number: 20230216501Abstract: A semiconductor device according to the present disclosure includes: a first output terminal and a second output terminal; a first driver that has a first positive terminal coupled to the first output terminal and a first negative terminal coupled to the second output terminal, and outputs a differential signal corresponding to a first signal from the first positive terminal and the first negative terminal; and a second driver that has a second positive terminal coupled to the second output terminal and a second negative terminal coupled to the first output terminal, and outputs a differential signal corresponding to the first signal from the second positive terminal and the second negative terminal.Type: ApplicationFiled: March 25, 2021Publication date: July 6, 2023Inventors: JUNICHIRO SHIRAI, HISASHI OWA
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Patent number: 11671086Abstract: A circuit system is disclosed. In one example, the circuit system includes a clock tree circuit with multiple lanes to which a clock signal is distributed. A duty correction circuit is provided for each of the multiple lanes, and corrects a duty ratio of the clock signal. A clock gating circuit group has a clock gating circuit for each of the multiple lanes and receives, as input, the clock signal from the duty correction circuit. The clock gating circuit group starts output of the clock signal from each of a plurality of the clock gating circuits in a predetermined period. A variable delay circuit is provided in association with each of a plurality of the duty correction circuits and is capable of changing a delay time of a control signal that controls a timing of starting output of the clock signal from the clock gating circuit.Type: GrantFiled: April 3, 2020Date of Patent: June 6, 2023Assignee: Sony Semiconductor Solutions CorporationInventors: Yuya Kimura, Hisashi Owa, Takashi Nakamura
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Publication number: 20220216860Abstract: A circuit system is disclosed. In one example, the circuit system includes a clock tree circuit with multiple lanes to which a clock signal is distributed. A duty correction circuit is provided for each of the multiple lanes, and corrects a duty ratio of the clock signal. A clock gating circuit group has a clock gating circuit for each of the multiple lanes and receives, as input, the clock signal from the duty correction circuit. The clock gating circuit group starts output of the clock signal from each of a plurality of the clock gating circuits in a predetermined period. A variable delay circuit is provided in association with each of a plurality of the duty correction circuits and is capable of changing a delay time of a control signal that controls a timing of starting output of the clock signal from the clock gating circuit.Type: ApplicationFiled: April 3, 2020Publication date: July 7, 2022Inventors: Yuya Kimura, Hisashi Owa, Takashi Nakamura
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Patent number: 10015026Abstract: A transmitter according to the disclosure includes: three first driver sections; three first pre-driver sections that are provided corresponding to the respective three first driver sections, and each drive corresponding one of the first driver sections on a basis of corresponding one of three first control signals that are different from one another and each including predetermined number of signals; a second pre-driver section that operates on a basis of a second control signal that includes predetermined number of signals; and a controller that controls transition of the predetermined number of signals included in the second control signal to allow number of signals to be subjected to the transition out of the plurality of signals included in the three first control signals and the plurality of signals included in the second control signal to be same between timings of the transition.Type: GrantFiled: September 25, 2015Date of Patent: July 3, 2018Assignee: Sony CorporationInventor: Hisashi Owa
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Publication number: 20170288920Abstract: A transmitter according to the disclosure includes: three first driver sections; three first pre-driver sections that are provided corresponding to the respective three first driver sections, and each drive corresponding one of the first driver sections on a basis of corresponding one of three first control signals that are different from one another and each including predetermined number of signals; a second pre-driver section that operates on a basis of a second control signal that includes predetermined number of signals; and a controller that controls transition of the predetermined number of signals included in the second control signal to allow number of signals to be subjected to the transition out of the plurality of signals included in the three first control signals and the plurality of signals included in the second control signal to be same between timings of the transition.Type: ApplicationFiled: September 25, 2015Publication date: October 5, 2017Applicant: Sony CorporationInventor: Hisashi Owa
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Patent number: 8467490Abstract: A communication system includes: a transmitter adapted to transmit a synchronizing clock and serial data synchronous with the synchronizing clock over a line at low amplitude; and a receiver adapted to receive the serial data and synchronizing clock from the transmitter. The receiver includes an amplifier adapted to amplify the received synchronizing clock of low amplitude to restore the clock to its original amplitude, a latched comparator adapted to latch the received serial data in synchronism with a reproduction clock, and a phase-locked circuit.Type: GrantFiled: March 11, 2009Date of Patent: June 18, 2013Assignee: Sony CorporationInventors: Takaaki Yamada, Hiroki Kihara, Tatsuya Sugioka, Hisashi Owa, Taichi Niki, Yukio Shimomura
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Publication number: 20090232250Abstract: A communication system includes: a transmitter adapted to transmit a synchronizing clock and serial data synchronous with the synchronizing clock over a line at low amplitude; and a receiver adapted to receive the serial data and synchronizing clock from the transmitter. The receiver includes an amplifier adapted to amplify the received synchronizing clock of low amplitude to restore the clock to its original amplitude, a latched comparator adapted to latch the received serial data in synchronism with a reproduction clock, and a phase-locked circuit.Type: ApplicationFiled: March 11, 2009Publication date: September 17, 2009Inventors: Takaaki YAMADA, Hiroki KIHARA, Tatsuya SUGIOKA, Hisashi OWA, Taichi NIKI, Yukio SHIMOMURA