Patents by Inventor Hisashi Terada

Hisashi Terada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10129846
    Abstract: An input unit inputs detected information that has been acquired by a sensor. By inserting time information into the detected information that has been input, a multiplexer generates an information sequence in which the detected information and the time information are multiplexed in a time-dividing manner. A transmission unit transmits the information sequence. The time information in the multiplexer is used to synchronize timing between detected information included in an information sequence transmitted from another transmitter and the detected information in the multiplexer.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: November 13, 2018
    Assignee: JVC KENWOOD Corporation
    Inventors: Atsushi Hayami, Hisashi Terada
  • Publication number: 20160255600
    Abstract: An input unit inputs detected information that has been acquired by a sensor. By inserting time information into the detected information that has been input, a multiplexer generates an information sequence in which the detected information and the time information are multiplexed in a time-dividing manner. A transmission unit transmits the information sequence. The time information in the multiplexer is used to synchronize timing between detected information included in an information sequence transmitted from another transmitter and the detected information in the multiplexer.
    Type: Application
    Filed: May 11, 2016
    Publication date: September 1, 2016
    Inventors: Atsushi HAYAMI, Hisashi TERADA
  • Patent number: 7182645
    Abstract: A card connector can selectively receive one of two IC cards. The card connector has an improved structure of contacts arranged in a card receiving space to simplify the structure thereof and to allow the card connector to be manufactured easily. The card connector at least includes a space for receiving a card and a plurality of contacts that are provided in the space parallel to the direction along which a card is inserted. The respective contacts provided in the space for receiving the IC card include a plurality of contact points that respectively correspond to the respective pads of the plurality of IC cards and that are provided in the direction along which the IC card is inserted. Thus, the card connector can be selectively attached with one of a plurality of IC cards having the same pad pitch.
    Type: Grant
    Filed: January 21, 2005
    Date of Patent: February 27, 2007
    Assignee: Yamaichi Electronics Co., Ltd.
    Inventors: Osamu Shimizu, Seiji Shishikura, Hisashi Terada
  • Publication number: 20050164559
    Abstract: A card connector can selectively receive one of two IC cards. The card connector has an improved structure of contacts arranged in a card receiving space to simplify the structure thereof and to allow the card connector to be manufactured easily. The card connector at least includes a space for receiving a card and a plurality of contacts that are provided in the space parallel to the direction along which a card is inserted. The respective contacts provided in the space for receiving the IC card include a plurality of contact points that respectively correspond to the respective pads of the plurality of IC cards and that are provided in the direction along which the IC card is inserted. Thus, the card connector can be selectively attached with one of a plurality of IC cards having the same pad pitch.
    Type: Application
    Filed: January 21, 2005
    Publication date: July 28, 2005
    Inventors: Osamu Shimizu, Seiji Shishikura, Hisashi Terada
  • Patent number: 5179574
    Abstract: A spread PN code signal receiver having a delay locked loop (DLL) circuit in an IF or RF stage characterized in that correlation outputs to be used for the DLL circuit control are (1) a correlation output between (a) a PN code advanced in phase with respect to the received signal and (b) the received signal and (2) a correlation output between (a) a PN code delayed in phase with respect to the received signal and (b) the received signal. The correlation outputs are used to detect the lock/unlock signal in the DLL circuit. In particular, AND logic for these two correlation outputs is employed to generate the lock/unlock signal only when the DLL circuit is perfectly synchronized in phase with the received signal. With this feature, a lock state can not de detected unitl a stable lock state is obtained.
    Type: Grant
    Filed: November 4, 1991
    Date of Patent: January 12, 1993
    Assignee: Kabushiki Kaisha Kenwood
    Inventors: Shintaro Watanabe, Yasushi Yamaguchi, Shigeyuki Nakayama, Hirotaka Namioka, Hisashi Terada
  • Patent number: 5090023
    Abstract: The correlation between a PN code pattern of the synchronization preamble data of an incoming spread spectrum signal and a reference PN code pattern generated on the reception side is detected by using an SAW convolver. The gate length of the SAW convolver is shorter than the preamble data length. However, an apparatus which can obtain the true correlation output by calculating the logical multiplication of the correlation output from the SAW convolver and the validation pulse is constituted.
    Type: Grant
    Filed: October 27, 1989
    Date of Patent: February 18, 1992
    Assignee: Kabushiki Kaisha Kenwood
    Inventors: Shintaro Watanabe, Yasushi Yamaguchi, Shigeyuki Nakayama, Hirotaka Namioka, Hisashi Terada
  • Patent number: 4942590
    Abstract: A clock generator in a data receiver for generating an optimum PN code clock used by a spectrum spread (55) communication receiver. The generator comprises a clock generator for generating a plurality of clocks having different phases; a synchronization signal detection circuit for detecting a synchronization signal within a received signal; an optimum clock discrimination circuit for discriminating a first active clock from the plurality of clocks after the synchronization signal detection circuit detected the synchronization signal; and a clock selection circuit for selecting and outputting the clock discriminated from the plurality of clocks by the optimum clock discrimination circuit.
    Type: Grant
    Filed: October 27, 1988
    Date of Patent: July 17, 1990
    Assignee: Kabushiki Kaisha Kenwood
    Inventor: Hisashi Terada