Abstract: In a clock recovery circuit for DTV using a VSB modulation method, if the frequency of the symbol clock is fs, since the frequency difference between the fs/2 component signal of the VSB signal and the pilot signal is constant at fs/2, it is possible accurately to detect the phase error from their differential signal. Furthermore there is no distortion of the clock signal frequency of the VSB signal, even when the symbol data is distorted by multi-pass distortion or the like, since clock signal regeneration is performed by frequency domain processing. By employing this type of principle and performing phase error detection for each symbol at a time, it is possible to ensure a high speed tracking performance for clock signal regeneration.

Abstract: An input signal DT contains a segment synchronization signal compliant with the ATSC standard. A clock multiplication section 111 multiplies a clock CK. A switchable sampling section 112 selects a sample point from among a plurality of timing points that are defined by the multiplied clock, and samples the input signal DT at the selected sample point. Moreover, the switchable sampling section 112 switches sample points from one to another in a synchronization-unestablished state. Once the segment synchronization is established, a synchronization detection device may maintain a synchronization-established state until the field synchronization detection fails, or the synchronization detection device may output a synchronization detection signal after shifting it in the time direction based on a bit error rate RT of the input signal.

Abstract: A synchronization error occurs when a DTV signal is distorted on a transmission path and this deteriorates demodulation capability. The digital demodulation device and the synchronization detecting method of the invention can correct the synchronization position when determining that a synchronization error has occurred. A controller receives a center tap coefficient, for example, from a waveform equalizer and compares the coefficient with a given center tap coefficient threshold. If the coefficient is smaller than the threshold, the controller determines that a synchronization detector has made a synchronization error and outputs a control signal. The synchronization detector receiving the control signal re-detects a sync signal included in a received signal, to detect a new correct sync signal and thus correct the synchronization error.

Abstract: An OFDM baseband signal that has undergone a synchronization carrier modulation or a differential carrier modulation is inputted to a complex signal converter for nonlinear distortion equalization so as to be converted according to the N-th order function conversion characteristics (N>1). Then, nonlinear distortion in the OFDM baseband signal is compensated for.

Abstract: A high power stripe-geometry heterojunction laser diode device is provided which may be employed in a radar system designed to measure the distance to a target. The laser diode device has an electric circuit path extending from a first electrode connected to a voltage source to a second electrode connected to ground and features addition of a resistance of 1 m&OHgr; or more to the electric circuit path to provide uniform current distribution in an active layer for emitting a high density laser beam.

Abstract: A digital demodulation apparatus is provided for automatically controlling gain based on a state of receiving a digital modulated signal.

Abstract: In a clock recovery circuit for DTV using a VSB modulation method, if the frequency of the symbol clock is fs, since the frequency difference between the fs/2 component signal of the VSB signal and the pilot signal is constant at fs/2, it is possible accurately to detect the phase error from their differential signal. Furthermore there is no distortion of the clock signal frequency of the VSB signal, even when the symbol data is distorted by multi-pass distortion or the like, since clock signal regeneration is performed by frequency domain processing. By employing this type of principle and performing phase error detection for each symbol at a time, it is possible to ensure a high speed tracking performance for clock signal regeneration.

Abstract: In an automatic gain control amplifier AGCa, an RF automatic gain controller 2 controls the gain of a radio frequency signal Srf. A frequency converter 3, 4 frequency-converts the radio frequency signal Srfa into an intermediate frequency signal Sifa. An IF automatic gain controller 5 controls the gain of the intermediate frequency Sifa. A level detector LDa detects a signal level of the gain-controlled intermediate frequency signal Sifa, and generates a level signal SLa. An automatic gain control signal generator SGa, SGb separately controls, based the level signal SLa, SLb, the RF automatic gain controller 2 and the IF automatic gain controller 5.

Abstract: A broadcast receiving apparatus provides multifunctionality to cope with analog modulated input signals as well as digital input signals modulated by various types of modulation schemes. The apparatus comprises a detector for detecting the modulation scheme of input signals, and a switch for switching one or more of the characteristic of a filtering section, an amplifying section, and a detection section, depending upon the detected modulated scheme.

Abstract: A Vestigal Sideband (VSB) demodulator having a clock generator for generating a clock signal based on a symbol frequency of the VSB signal; an A/D converter for converting the VSB signal into a digital signal based on the clock signal of the clock generator; a first multiplier for multiplying the digital signal by a first value sequence and generating a first multiplier output signal; a second multiplier for multiplying the digital signal by a second value sequence and generating a second multiplier output signal; a complex type filter for shaping and VSB demodulation of the multiplier output signals and generating Inphase and Quadrature data output signals; a decimating circuit for decimating the Inphase and Quadrature data output signals and generating decimated signals; a complex multiplier for multiplying the decimated signals by a predetermined value and generating multiplied output signals; an error detector for detecting a frequency deviation and a phase deviation from the multiplied output signals and