Abstract: Bi-directional buffer circuit comprises a second P-channel transistor whose back gate is connected to a pad, a third P-channel transistor disposed between a gate of the second P-channel transistor and the pad with its back gate connected to the pad, and a first N-channel transistor and a fifth N-channel transistor whose gates are connected to a power source, so that an output buffer circuit, an input buffer circuit and a bi-directional buffer circuit can be produced without necessity of any additional processing step, wherein merely a single power source is incorporated, and a voltage higher than the source voltage is permitted to be applied to a common bus.

Abstract: In selectors 21.sub.0 -21.sub.3 two pull-up switching elements 40-40.sub.3, 42.sub.0 -42.sub.3, the elements being connected in series to each other in each selector, are additionally provided instead of a don't care-setting two-input NAND gate, for connecting or disconnecting connection lines of outputs of positive logic switching elements 24.sub.0 -24.sub.3 and those of negative logic switching elements 23.sub.0 -23.sub.3 with or from a power supply line Vdd. First memory cells M.sub.00 -M.sub.30 control on-off states of negative logic switching elements 23.sub.0 -23.sub.3 and ones 40.sub.0 -40.sub.3 of pull-up switching elements, and second memory cells M.sub.01 -M.sub.31 control on-off states of positive logic switching elements 24.sub.0 -24.sub.3 and the others 42.sub.1 -42.sub.3 of the pull-up switching elements. Thus, use of a prior art two-input NAND gate is eliminated and hence the number of transistors is reduced.

Abstract: A required number of coincidence detecting circuits for the combinations of N input signals are provided, so that useless PLEs as seen in a table lookup type are eliminated. Product term lines of PLA are extended by a first extension circuit. Similarly, respective coincidence detecting outputs of coincidence detecting circuits of another PLE are connected to each other, so that coincidence signals can be output in association with M (.gtoreq.N) input signals. Coincidence detecting signals of further PLE are connected by a second extension circuit, whereby the number of storing of combinations of N or M input signals is extended to P sets or more, so that the number of input signals N can be set at a low value. There are added programmable selectors for making some of input signals into the coincidence detecting circuits replaceable with other input signals, so that the operating efficiency of PLE can be improved.

Abstract: In a programmable logic device having a plurality of programmable logic elements (PLEs) where each PLE includes a combinational logic circuit and a plurality of flip-flop circuits, input selector switches for selecting one of a plurality of input signals to be input into a flip-flop circuit are provided by which an output from a combinational logic circuit of its own PLE and an output from another PLE are made selectable. The output from the combinational logic circuit is also output independently of an output from a flip-flop circuit, so that either one of the outputs can be utilized by use of external programmble wiring. Further by selecting respective input terminals of each flip-flop circuit, an output signal from an adjoining flip-flop circuit is inputtable into another flip-flop circuit, so that the flip-flop circuits can be serially connected to each other.