Patents by Inventor Hisayo S. Momose

Hisayo S. Momose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5489542
    Abstract: A method for fabricating a semiconductor device on a silicon substrate, consists of producing a silicon oxide film on the silicon substrate producing a thin silicon nitride film on the silicon oxide film, thermally nitriding the silicon nitride film in an atmosphere of nitrogenous gas, producing a conductive film on the silicon nitride film nitrided in the atmosphere of the nitrogenous gas, producing a gate region from the silicon oxide film, the silicon nitride film, and the conductive film, a channel region being positioned under the gate region in the silicon substrate, producing a source region in the silicon substrate adjacent to one side of the channel region, producing a drain region in the silicon substrate adjacent to another side of the channel region, and producing wiring regions on the source region, the drain region, and the gate region.
    Type: Grant
    Filed: July 16, 1993
    Date of Patent: February 6, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Iwai, Toyota Morimoto, Hisayo S. Momose, Kikuo Yamabe, Yoshio Ozawa
  • Patent number: 5237188
    Abstract: A semiconductor device formed on a silicon substrate consisting of the steps of producing a silicon oxide film on the silicon substrate, producing a thin silicon nitride film on the silicon oxide film, thermally nitriding the silicon nitride film in an atmosphere of nitrogenous gas, producing a conductive film on the silicon nitride film nitrided in the atmosphere of the nitrogenous gas, producing a gate region from the silicon oxide film, the silicon nitride film, and the conductive film, a channel region being positioned under the gate region in the silicon substrate, producing a source region in the silicon substrate adjacent to one side of the channel region, producing a drain region in the silicon substrate adjacent to another side of the channel region, and producing wiring regions on the source region, the drain region, and the gate region.
    Type: Grant
    Filed: November 27, 1991
    Date of Patent: August 17, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Iwai, Toyota Morimoto, Hisayo S. Momose, Kikuo Yamabe, Yoshio Ozawa
  • Patent number: 5227855
    Abstract: An insulating layer is formed on a transistor having a source region/drain region and a gate electrode. Contact holes are formed in this insulating layer in association with the source region/drain region and the gate electrode. A memory element having a ferroelectric substance layer is provided in that contact hole which is associated with the source region/drain region. This memory element comprises a first electrode provided on the source region/drain region, a ferroelectric substance layer provided on the first electrode, and a second electrode provided on the ferroelectric substance layer. Providing this memory element in the contact hole which is associated with the source region/drain region can make cells flatter and permit metal wires to be surely formed in the contact holes.
    Type: Grant
    Filed: January 23, 1991
    Date of Patent: July 13, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hisayo S. Momose