Patents by Inventor Hiten Advani
Hiten Advani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11799480Abstract: A circuit to multiplex supply voltages may include a set of chains of transistors. Each chain of transistors may correspond to a voltage supply that is desired to be multiplexed and may include a set of transistors coupled in series. A first end terminal of each chain of transistors may be coupled to a corresponding voltage supply, and a second end terminal of each chain of transistors may be coupled to an output terminal of the circuit. A given supply voltage may be selected by turning on transistors in a chain of transistors that corresponds to the given supply voltage and turning off transistors in other chains of transistors.Type: GrantFiled: December 3, 2021Date of Patent: October 24, 2023Assignee: Synopsys, Inc.Inventors: Akshay Adlakha, Hiten Advani
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Patent number: 10298119Abstract: According to an embodiment, a circuit includes a protection voltage generator coupled to a first voltage node, a second voltage node, and a ground voltage node, the protection voltage generator configured to generate a plurality of protection voltages at a first plurality of nodes based on the first voltage node and the second voltage node, and a voltage protection ladder coupled between the first voltage node and a low voltage circuit, the voltage protection ladder coupled to the plurality of protection voltages at the first plurality of nodes, the voltage protection ladder configured to generate a first low voltage based on the first voltage node and the plurality of protection voltages.Type: GrantFiled: November 7, 2017Date of Patent: May 21, 2019Assignee: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Phalguni Bala, Hiten Advani
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Publication number: 20180062506Abstract: According to an embodiment, a circuit includes a protection voltage generator coupled to a first voltage node, a second voltage node, and a ground voltage node, the protection voltage generator configured to generate a plurality of protection voltages at a first plurality of nodes based on the first voltage node and the second voltage node, and a voltage protection ladder coupled between the first voltage node and a low voltage circuit, the voltage protection ladder coupled to the plurality of protection voltages at the first plurality of nodes, the voltage protection ladder configured to generate a first low voltage based on the first voltage node and the plurality of protection voltages.Type: ApplicationFiled: November 7, 2017Publication date: March 1, 2018Inventors: Phalguni Bala, Hiten Advani
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Patent number: 9831764Abstract: According to an embodiment, a circuit includes a protection voltage generator coupled to a first voltage node, a second voltage node, and a ground voltage node, the protection voltage generator configured to generate a plurality of protection voltages at a first plurality of nodes based on the first voltage node and the second voltage node, and a voltage protection ladder coupled between the first voltage node and a low voltage circuit, the voltage protection ladder coupled to the plurality of protection voltages at the first plurality of nodes, the voltage protection ladder configured to generate a first low voltage based on the first voltage node and the plurality of protection voltages.Type: GrantFiled: November 20, 2014Date of Patent: November 28, 2017Assignee: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Phalguni Bala, Hiten Advani
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Publication number: 20160149491Abstract: According to an embodiment, a circuit includes a protection voltage generator coupled to a first voltage node, a second voltage node, and a ground voltage node, the protection voltage generator configured to generate a plurality of protection voltages at a first plurality of nodes based on the first voltage node and the second voltage node, and a voltage protection ladder coupled between the first voltage node and a low voltage circuit, the voltage protection ladder coupled to the plurality of protection voltages at the first plurality of nodes, the voltage protection ladder configured to generate a first low voltage based on the first voltage node and the plurality of protection voltages.Type: ApplicationFiled: November 20, 2014Publication date: May 26, 2016Inventors: Phalguni Bala, Hiten Advani
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Patent number: 9178418Abstract: An embodiment of a pre-emphasis circuit, an embodiment of a method for pre-emphasizing complementary single-ended signals, an embodiment of a transmitter, and an embodiment of a communication system.Type: GrantFiled: July 31, 2014Date of Patent: November 3, 2015Assignee: STMicroelectronics International N.V.Inventors: Manohar Raju K.S.V., Hiten Advani
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Patent number: 9106219Abstract: An embodiment includes an impedance calibration circuit having a calibrator configured to compare voltage levels at an external node and an internal node of the impedance calibration circuit and to generate an output based on the comparison. The calibrator further includes respective filters coupled between the external node and a first input of the comparator, and between the internal node and a second input of the comparator. The filters are configured for symmetric noise injection into the comparator from a chip ground line to which a programmable resistor at the internal node is coupled.Type: GrantFiled: November 8, 2013Date of Patent: August 11, 2015Assignee: STMicroelectronics International N.V.Inventors: Mayank Kumar Singh, Daljeet Kumar, Hiten Advani
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Publication number: 20140339894Abstract: An embodiment of a pre-emphasis circuit, an embodiment of a method for pre-emphasizing complementary single-ended signals, an embodiment of a transmitter, and an embodiment of a communication system.Type: ApplicationFiled: July 31, 2014Publication date: November 20, 2014Inventors: ManoharRaju K.S.V., Hiten ADVANI
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Patent number: 8823421Abstract: An embodiment of a pre-emphasis circuit, an embodiment of a method for pre-emphasizing complementary single-ended signals, an embodiment of a transmitter, and an embodiment of a communication system.Type: GrantFiled: September 23, 2011Date of Patent: September 2, 2014Assignee: STMicroelectronics International N.V.Inventors: ManoharRaju K.S.V., Hiten Advani
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Patent number: 8686754Abstract: A system and method for utilizing multiple configurable lanes for clock and data transfer in source synchronous systems that may utilize a clock signal from another source for interpreting data received from the source. In an embodiment, a system may include a transmitter configured to transmit at least one clock signal and at least one data signal to a receiver device. The receiver device may have at least one clock lane and at least one data lane for receiving signals from the transmitter device. The clock lane(s) and data lane(s) can be arranged in any order as per requirement of system design. In the receiver, after manufacture, each data lane may be configured to be clocked by any clock lane.Type: GrantFiled: July 5, 2012Date of Patent: April 1, 2014Assignee: STMicroelectronics International N.V.Inventors: Sanjeev Chopra, Hiten Advani
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Patent number: 8681534Abstract: A memory cell is formed by storage latch having a true node and a complement node. The cell includes a write port operable in response to a write signal on a write word line to write data from write bit lines into the latch, and a separate read port operable in response to a read signal on a read word line to read data from the latch to a read bit line. The circuitry of the memory cell is configured to address voltage bounce at the complement node during reading of the memory (where the voltage bounce arises from a simultaneous write to another memory cell in a same row).Type: GrantFiled: December 29, 2011Date of Patent: March 25, 2014Assignee: STMicroelectronics International N.V.Inventors: Nishu Kohli, Hiten Advani
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Publication number: 20140070843Abstract: An embodiment includes an impedance calibration circuit having a calibrator configured to compare voltage levels at an external node and an internal node of the impedance calibration circuit and to generate an output based on the comparison. The calibrator further includes respective filters coupled between the external node and a first input of the comparator, and between the internal node and a second input of the comparator. The filters are configured for symmetric noise injection into the comparator from a chip ground line to which a programmable resistor at the internal node is coupled.Type: ApplicationFiled: November 8, 2013Publication date: March 13, 2014Applicant: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Mayank Kumar SINGH, Daljeet KUMAR, Hiten ADVANI
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Publication number: 20140009633Abstract: A system and method for utilizing multiple configurable lanes for clock and data transfer in source synchronous systems that may utilize a clock signal from another source for interpreting data received from the source. In an embodiment, a system may include a transmitter configured to transmit at least one clock signal and at least one data signal to a receiver device. The receiver device may have at least one clock lane and at least one data lane for receiving signals from the transmitter device. The clock lane(s) and data lane(s) can be arranged in any order as per requirement of system design. In the receiver, after manufacture, each data lane may be configured to be clocked by any clock lane.Type: ApplicationFiled: July 5, 2012Publication date: January 9, 2014Applicant: STMICROELECTRONICS PVT. LTDInventors: Sanjeev CHOPRA, Hiten ADVANI
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Patent number: 8581619Abstract: An embodiment includes an impedance calibration circuit having a calibrator configured to compare voltage levels at an external node and an internal node of the impedance calibration circuit and to generate an output based on the comparison. The calibrator further includes respective filters coupled between the external node and a first input of the comparator, and between the internal node and a second input of the comparator. The filters are configured for symmetric noise injection into the comparator from a chip ground line to which a programmable resistor at the internal node is coupled.Type: GrantFiled: August 25, 2011Date of Patent: November 12, 2013Assignee: STMicroelectronics International N.V.Inventors: Mayank Kumar Singh, Daljeet Kumar, Hiten Advani
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Publication number: 20130170288Abstract: A memory cell is formed by storage latch having a true node and a complement node. The cell includes a write port operable in response to a write signal on a write word line to write data from write bit lines into the latch, and a separate read port operable in response to a read signal on a read word line to read data from the latch to a read bit line. The circuitry of the memory cell is configured to address voltage bounce at the complement node during reading of the memory (where the voltage bounce arises from a simultaneous write to another memory cell in a same row).Type: ApplicationFiled: December 29, 2011Publication date: July 4, 2013Applicant: STMICROELECTRONICS PVT. LTD.Inventors: Nishu KOHLI, Hiten ADVANI
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Publication number: 20130049797Abstract: An embodiment of an impedance calibration circuit and method, a device including an impedance calibration circuit, and a transmission link system.Type: ApplicationFiled: August 25, 2011Publication date: February 28, 2013Applicant: STMicronelectronics Pvt. Ltd.Inventors: Mayank Kumar SINGH, Daljeet KUMAR, Hiten ADVANI
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Publication number: 20130003882Abstract: An embodiment of a pre-emphasis circuit, an embodiment of a method for pre-emphasizing complementary single-ended signals, an embodiment of a transmitter, and an embodiment of a communication system.Type: ApplicationFiled: September 23, 2011Publication date: January 3, 2013Applicant: STMICROELECTRONICS PVT. LTD.Inventors: ManoharRaju K.S.V., Hiten ADVANI
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Patent number: 7380230Abstract: An improved timing skew measurement system includes a selector receiving a plurality of input signals whose relative skew is to be measured, a selection controller connected to the select inputs of the selector for selecting one of the input signals and a sequential logic element having a first input connected to the output of the selector. The system further includes a controllable clock generator capable of providing an adjustable clock edge position connected to a second input of the sequential logic element, the first and second inputs being associated by at least one defined timing relationship for correct operation of the sequential logic element, and an output analyzer having one input connected to the output of the sequential logic element, a first output connected to the input of the selection controller and a second output connected to the control input of the controllable clock generator.Type: GrantFiled: September 6, 2005Date of Patent: May 27, 2008Assignee: STMicroelectronics Pvt. Ltd.Inventor: Hiten Advani
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Publication number: 20060136853Abstract: An improved timing skew measurement system includes a selector receiving a plurality of input signals whose relative skew is to be measured, a selection controller connected to the select inputs of the selector for selecting one of the input signals and a sequential logic element having a first input connected to the output of the selector. The system further includes a controllable clock generator capable of providing an adjustable clock edge position connected to a second input of the sequential logic element, the first and second inputs being associated by at least one defined timing relationship for correct operation of the sequential logic element, and an output analyzer having one input connected to the output of the sequential logic element, a first output connected to the input of the selection controller and a second output connected to the control input of the controllable clock generator.Type: ApplicationFiled: September 6, 2005Publication date: June 22, 2006Applicant: STMicroelectronics Pvt. Ltd.Inventor: Hiten Advani