Patents by Inventor Hitesh Mohan Kumar

Hitesh Mohan Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11941334
    Abstract: Embodiments include herein are directed towards a system and method for intelligent intent recognition based electronic design. Embodiments may include receiving, using a processor, a natural language input from a user at an intent recognition model. Embodiments may also include performing intent recognition on the natural language input at the intent recognition model and providing an output from the intent recognition model to a command generator. Embodiments may further include generating a command based upon, at least in part, the output and executing the command at a target tool environment.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: March 26, 2024
    Assignee: Cadence Design Systems, Inc.
    Inventors: Deepak Gupta, Hitesh Mohan Kumar, Yatinder Singh
  • Patent number: 11270050
    Abstract: The present disclosure relates to a method for use with an electronic design. Embodiments may include displaying, at a graphical user interface, at least a portion of the electronic design and receiving a selection of a subcircuit at a first position of the graphical user interface. In response to a user input, embodiments may include transitioning the subcircuit from the first position to a second position of the graphical user interface and determining one or more direct and indirect connections resulting from a potential placement at the second position. Embodiments may include determining an influence metric by applying an optimized connectivity rules definition upon the potential placement at the second position and the one or more direct and indirect connections. Embodiments may also include displaying feedback at the graphical user interface based upon, at least in part, the influence metric.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: March 8, 2022
    Assignee: Cadence Design Systems, Inc.
    Inventors: Hitesh Mohan Kumar, Anuj Jain, Sahil Vij, Abhimanyu Bhowmik, Rahul Kumar
  • Patent number: 10558774
    Abstract: The present embodiments are generally directed to electronic circuit design and verification and more particularly to techniques for generating electronic design element symbols for electronic circuit design tool libraries and designs in any desired format. In embodiments, such electronic design element symbols can be generated from a datasheet or any other image using image processing, graphical shape and text recognition techniques. Embodiments use step by step processing to extract feature vectors from a symbol/design image, apply text and graphical shapes recognition using models, apply techniques for data association and write the final output for targeted systems. These and other embodiments can feed back the output data for further refinement of the recognition models.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: February 11, 2020
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Hitesh Mohan Kumar, Raghav Sharma
  • Patent number: 10289788
    Abstract: The present disclosure relates to a computer-implemented method for electronic design automation. Embodiments may include storing one or more electronic circuit designs at an electronic circuit design database and receiving a user input associated with one of the electronic circuit designs. Embodiments may include scanning the one or more stored electronic circuit designs and generating a network including a relationship graph and a component map, based upon, at least in part, the scanning Embodiments may include generating at least one next neighbor component based upon, at least in part, the network and the received user input. Embodiments may include displaying one or more user-selectable options at a graphical user interface, wherein the user-selectable options include the at least one next neighbor component.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: May 14, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Hitesh Mohan Kumar, Matthew Timothy Bromley, Vikas Kohli, Sagar Kumar
  • Patent number: 9645715
    Abstract: The present disclosure relates to a computer-implemented method for electronic design simulation. The method may include receiving, using at least one processor, an electronic design and displaying, at a graphical user interface, at least a portion of the electronic design. Embodiments may also include allowing a user to select at least one design variable at the graphical user interface. Embodiments may also include simulating the electronic design, based upon, at least in part, the selected at least one design variable and in response to the simulation, automatically displaying an updated value at the graphical user interface.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: May 9, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Abha Jain, Hitesh Mohan Kumar, Parag Choudhary, Viren Agarwal
  • Patent number: 9633163
    Abstract: The present disclosure relates to a computer-implemented method for electronic design automation. The method may include providing, using one or more processors, an electronic design and visually displaying a plurality of possible route sets associated with the electronic design at a graphical user interface. The method may include providing an option to select between the plurality of possible route sets at the graphical user interface.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: April 25, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Hitesh Mohan Kumar, Sagar Kumar, Ankur Gupta
  • Patent number: 8427502
    Abstract: A graphical editor displays graphical representations of underlying data items in a distribution of information-bearing states across a bounded region of a display. One or more of the data items are selected as belonging to a context of a user task or operation. The information-bearing states are redistributed in the bounded region of the display so that an amount of information sufficient to the task is provided through the graphical representations of the data items in the context and any space in the bounded region of the display needed to display such information is acquired by a decrease in the amount of information provided by the data items outside the context.
    Type: Grant
    Filed: August 8, 2008
    Date of Patent: April 23, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Parag Choudhary, Hitesh Mohan Kumar, Abha Jain
  • Publication number: 20100037136
    Abstract: A graphical editor displays graphical representations of underlying data items in a distribution of information-bearing states across a bounded region of a display. One or more of the data items are selected as belonging to a context of a user task or operation. The information-bearing states are redistributed in the bounded region of the display so that an amount of information sufficient to the task is provided through the graphical representations of the data items in the context and any space in the bounded region of the display needed to display such information is acquired by a decrease in the amount of information provided by the data items outside the context.
    Type: Application
    Filed: August 8, 2008
    Publication date: February 11, 2010
    Applicant: CADENCE DESIGN SYSTEMS, INC
    Inventors: Parag Choudhary, Hitesh Mohan Kumar, Abha Jain