Patents by Inventor Hitomi Yamaguchi
Hitomi Yamaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11945509Abstract: A vehicle body rear part structure includes a rear frame and a beam member. The rear frame has: a first inner bead, a first outer bead, a second inner bead, and a second outer bead. The first inner bead and the first outer bead are formed on an inner wall and an outer wall, respectively, in a region close to the beam member. The second inner bead and the second outer bead are formed on the inner wall and the outer wall, respectively, in a region that is separated to a vehicle body frontward direction from the first beads. The first outer bead is formed to have a higher fragility than the first inner bead.Type: GrantFiled: January 26, 2022Date of Patent: April 2, 2024Assignee: HONDA MOTOR CO., LTD.Inventors: Shungo Chino, Yuya Akaba, Toshihiro Yamaguchi, Kyosuke Yamakita, Yusuke Miura, Dai Kamata, Chihiro Sakagami, Kosuke Fushimi, Shohei Ohtsuka, Hitomi Yamada
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Patent number: 11721520Abstract: A semiconductor device according to an embodiment includes: a substrate including a plurality of through holes provided at predetermined intervals along a first direction in a substrate surface and along a second direction intersecting the first direction in the substrate surface; an insulating layer provided on the substrate, the insulating layer being penetrated by the through holes; a plurality of first electrodes provided on the insulating layer, the first electrodes being adjacent to the respective through holes in the first direction; a plurality of second electrodes provided on the insulating layer, the second electrodes being adjacent to the respective through holes in the first direction, the second electrodes being provided to face the first electrodes, the second electrodes being held at a predetermined potential; and a wiring layer provided on the insulating layer, the wiring layer electrically connecting the adjacent second electrodes.Type: GrantFiled: January 21, 2022Date of Patent: August 8, 2023Assignee: NuFlare Technology, Inc.Inventors: Kei Obara, Kazuyuki Higashi, Miyoko Shimada, Yoshiaki Shimooka, Hitomi Yamaguchi, Yoshikuni Goshima, Hirofumi Morita, Hiroshi Matsumoto
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Publication number: 20220270850Abstract: A semiconductor device according to an embodiment includes: a substrate including a plurality of through holes provided at predetermined intervals along a first direction in a substrate surface and along a second direction intersecting the first direction in the substrate surface; an insulating layer provided on the substrate, the insulating layer being penetrated by the through holes; a plurality of first electrodes provided on the insulating layer, the first electrodes being adjacent to the respective through holes in the first direction; a plurality of second electrodes provided on the insulating layer, the second electrodes being adjacent to the respective through holes in the first direction, the second electrodes being provided to face the first electrodes, the second electrodes being held at a predetermined potential; and a wiring layer provided on the insulating layer, the wiring layer electrically connecting the adjacent second electrodes.Type: ApplicationFiled: January 21, 2022Publication date: August 25, 2022Applicant: NuFlare Technology, Inc.Inventors: Kei OBARA, Kazuyuki HIGASHI, Miyoko SHIMADA, Yoshiaki SHIMOOKA, Hitomi YAMAGUCHI, Yoshikuni GOSHIMA, Hirofumi MORITA, Hiroshi MATSUMOTO
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Patent number: 10039302Abstract: Provided is a frozen pasta retaining an original flavor of the pasta. A frozen pasta attached with a ground pasta product and/or durum wheat flour. A process for producing a frozen pasta, comprising cooling a boiled pasta and attaching, to the surface of the pasta, a ground product of a pasta, followed by freezing.Type: GrantFiled: May 11, 2012Date of Patent: August 7, 2018Assignee: NISSHIN FOODS INC.Inventors: Youichirou Miya, Hitomi Yamaguchi, Fusaki Kajio
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Publication number: 20170077215Abstract: According to one embodiment, an electronic device includes a first element provided on a semiconductor substrate and used for actual operation, and a second element unit constituted by at least one second element for evaluation provided on the semiconductor substrate, wherein the first element includes a first plate-like portion and a first thin-film portion covering the first plate-like portion and forming a cavity therein, and the second element unit includes a plurality of second plate-like portions having different lengths, and at least one second thin-film portion covering the second plate-like portions and forming a cavity therein.Type: ApplicationFiled: March 11, 2016Publication date: March 16, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Hitomi YAMAGUCHI
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Publication number: 20160198743Abstract: This method for producing cooked fresh pasta with a sauce involves: a fresh pasta preparation step of preparing a dough by adding water to a raw material flour, obtaining a fresh pasta by extruding the dough at a pressure of from 35 to 100 kgf/cm2, and subjecting the fresh pasta to a dry heating treatment to adjust the mass of the fresh pasta after the treatment to 80 to 97 mass % with respect to the mass of the fresh pasta before the treatment; and a cooking step of obtaining cooked fresh pasta by boil-cooking or steam-cooking the fresh pasta after the dry heating treatment. Preferably, the raw material flour contains an emulsifier, and a flour material including wheat flour as a main component; and the content of the emulsifier is from 0.2 to 2 parts by mass with respect to 100 parts by mass of the flour material.Type: ApplicationFiled: September 25, 2014Publication date: July 14, 2016Inventors: Youhei SUGA, Hitomi YAMAGUCHI, Youichirou MIYA, Takenori WATANABE
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Publication number: 20160007637Abstract: A frozen gratin production method involves: obtaining fresh pasta by extruding a dough including durum wheat flour at a pressure of from 100 to 200 kgf/cm2; boiling and cooking the fresh pasta; and then freezing the boiled-and-cooked fresh pasta together with a sauce. It is suitable to use, as the aforementioned dough, a dough including from 2 to 6 parts by mass of a vegetable protein with respect to 100 parts by mass of the durum wheat flour. It is also suitable to boil and cook the fresh pasta such that the yield-after-boiling of the fresh pasta is from 190% to 250%.Type: ApplicationFiled: March 24, 2014Publication date: January 14, 2016Inventors: Hitomi YAMAGUCHI, Youhei SUGA, Takenori WATANABE, Youichiro MIYA
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Publication number: 20150259192Abstract: According to one embodiment, a MEMS device is disclosed. The device includes a substrate, a MEMS element as a first component provided on the substrate, a first film having a plurality of through holes. The first film and the substrate are configured to form a cavity accommodating the MEMS element. The device further includes a second film provided on the first film, a second component provided on the substrate and disposed outside of the cavity, and a film provided on the substrate and disposed outside of the cavity, and configured to surround the second component.Type: ApplicationFiled: August 26, 2014Publication date: September 17, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hitomi YAMAGUCHI, Yoshiaki SHIMOOKA, Tsuyoshi HIRAYU, Kiyonori IGARASHI
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Publication number: 20150118364Abstract: Provided is a frozen pasta retaining an original flavor of the pasta. A frozen pasta attached with a ground pasta product and/or durum wheat flour. A process for producing a frozen pasta, comprising cooling a boiled pasta and attaching, to the surface of the pasta, a ground product of a pasta, followed by freezing.Type: ApplicationFiled: May 11, 2012Publication date: April 30, 2015Applicant: NISSHIN FOODS INC.Inventors: Youichirou Miya, Hitomi Yamaguchi, Fusaki Kajio
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Publication number: 20140227419Abstract: The present invention provides an anti-fungal agent for processed cereal foods, and the anti-fungal agent contains chitinase. The present invention also provides an anti-fungal agent-containing processed cereal food, which contains the anti-fungal agent. The present invention further provides a method for producing an anti-fungal agent-containing processed cereal food. With the present invention, a safe and inexpensive anti-fungal agent for processed cereal foods is provided.Type: ApplicationFiled: October 2, 2012Publication date: August 14, 2014Applicants: NAGASE CHEMTEX CORPORATION, NAGASE & CO. LTDInventors: Naoki Shirasaka, Hitomi Yamaguchi
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Publication number: 20100185259Abstract: A garment for electrically stimulating muscles is provided to be used for, e.g., rehabilitation or exercise whereby an electrode can be conveniently provided at such a position as allowing the electrode to stimulate the nerve-muscular junction of a muscle to be moved in toning up the muscle through electrical stimulation on the muscle by taking advantage of the muscular contraction caused by electrically stimulating the muscle.Type: ApplicationFiled: June 25, 2008Publication date: July 22, 2010Applicants: Kurume University, Kyushu Institute of Technology, Sekisui Plastics Co. , Ltd., Japan Aerospace Ecploration Agency, Japann Space ForumInventors: Naoto Shiba, Hitomi Yamaguchi, Yoshihiko Tagawa, Kiyoshi Numada, Kazuhiro Yoshikawa, Keiji Murakami, Hajime Takeoka
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Publication number: 20080272494Abstract: A semiconductor device is provided, including: a first barrier metal film provided by a PVD process in a recess formed in at least one insulating film, and containing at least one metal element belonging to any of the groups 4-A, 5-A, and 6-A; a second barrier metal film continuously provided by at least one of CVD and ALD processes on the first barrier metal film without being opened to atmosphere, and containing at least one metal element belonging to any one of the groups 4-A, 5-A, and 6-A; a third barrier metal film continuously provided by the PVD process on the second barrier metal film without being opened to the atmosphere, and containing at least one metal element belonging to any one of the groups 4-A, 5-A, and 6-A; and a first Cu film continuously provided on the third barrier metal film without being opened to the atmosphere and thereafter heated.Type: ApplicationFiled: July 8, 2008Publication date: November 6, 2008Applicant: Kabushiki Kaisha ToshibaInventors: Seiichi Omoto, Tomio Katata, Kazuyuki Higashi, Hitomi Yamaguchi, Hirokazu Ezawa, Atsuko Sakata
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Patent number: 7399706Abstract: There is here disclosed a manufacturing method of a semiconductor device, comprising providing a first film by a PVD process in a recess formed in at least one insulating film, the first film containing at least one metal element belonging to any one of the groups 4-A, 5-A, and 6-A, continuously providing a second film by at least one of CVD and ALD processes on the first film without opening to atmosphere, the second film containing at least one metal element belonging to any one of the groups 4-A, 5-A, and 6-A, continuously providing a third film by the PVD process on the second film without opening to the atmosphere, the third film containing at least one metal element belonging to any one of the groups 4-A, 5-A, and 6-A, continuously providing a first Cu film on the third film without opening to the atmosphere, and heating the Cu film.Type: GrantFiled: January 25, 2005Date of Patent: July 15, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Seiichi Omoto, Tomio Katata, Kazuyuki Higashi, Hitomi Yamaguchi, Hirokazu Ezawa, Atsuko Sakata
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Patent number: 7135722Abstract: A semiconductor device is the semiconductor device which includes more than one field effect transistor having a gate electrode to which an electrical interconnect wire is connected and a gate insulation film with a thickness of 6.0 nm or less and which comprises a first transistor group made up of a plurality of field effect transistors that are the same in thickness of gate insulation film, a second transistor group made up of a plurality of field effect transistors that are the same in thickness of gate insulation film with the thickness of gate insulation film being less than the thickness of the gate insulation film of the first transistor group, and a semiconductor substrate on which the first and second transistor groups are mounted together in a mixed manner, wherein an antenna ratio which is a ratio of the area of a wire to the gate area of a gate electrode is such that the maximum value of the second transistor group is greater than the maximum value of the first transistor group.Type: GrantFiled: June 14, 2004Date of Patent: November 14, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Noriaki Matsunaga, Hitomi Yamaguchi
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Publication number: 20050186793Abstract: There is here disclosed a manufacturing method of a semiconductor device, comprising providing a first film by a PVD process in a recess formed in at least one insulating film, the first film containing at least one metal element belonging to any one of the groups 4-A, 5-A, and 6-A, continuously providing a second film by at least one of CVD and ALD processes on the first film without opening to atmosphere, the second film containing at least one metal element belonging to any one of the groups 4-A, 5-A, and 6-A, continuously providing a third film by the PVD process on the second film without opening to the atmosphere, the third film containing at least one metal element belonging to any one of the groups 4-A, 5-A, and 6-A, continuously providing a first Cu film on the third film without opening to the atmosphere, and heating the Cu film.Type: ApplicationFiled: January 25, 2005Publication date: August 25, 2005Inventors: Seiichi Omoto, Tomio Katata, Kazuyuki Higashi, Hitomi Yamaguchi, Hirokazu Ezawa, Atsuko Sakata
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Publication number: 20050051803Abstract: A semiconductor device is the semiconductor device which includes more than one field effect transistor having a gate electrode to which an electrical interconnect wire is connected and a gate insulation film with a thickness of 6.0 nm or less and which comprises a first transistor group made up of a plurality of field effect transistors that are the same in thickness of gate insulation film, a second transistor group made up of a plurality of field effect transistors that are the same in thickness of gate insulation film with the thickness of gate insulation film being less than the thickness of the gate insulation film of the first transistor group, and a semiconductor substrate on which the first and second transistor groups are mounted together in a mixed manner, wherein an antenna ratio which is a ratio of the area of a wire to the gate area of a gate electrode is such that the maximum value of the second transistor group is greater than the maximum value of the first transistor group.Type: ApplicationFiled: June 14, 2004Publication date: March 10, 2005Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Noriaki Matsunaga, Hitomi Yamaguchi
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Publication number: 20020106424Abstract: A natural food material with a high content of &ggr;-aminobutyric acid is provided, without any additional glutamic acid separately prepared, by treating a glutamine-containing raw material with glutamic acid decarboxylase and glutaminase so that &ggr;-aminobutyric acid can be produced not only from the glutamic acid but also from glutamine in the raw material. Also, a natural food material with a high content of &ggr;-aminobutyric acid is easily and effectively provided with using a typical production process by catalyzing the reaction with a microorganism having the activity of glutamic acid decarboxylase, which is provided as an enzyme of glutamic acid decarboxylase.Type: ApplicationFiled: February 5, 2002Publication date: August 8, 2002Applicant: KIKKOMAN CORPORATIONInventors: Yoshihiro Ogawa, Hitomi Yamaguchi, Youko Shimaoka
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Patent number: RE43945Abstract: A semiconductor device is the semiconductor device which includes more than one field effect transistor having a gate electrode to which an electrical interconnect wire is connected and a gate insulation film with a thickness of 6.0 nm or less and which comprises a first transistor group made up of a plurality of field effect transistors that are the same in thickness of gate insulation film, a second transistor group made up of a plurality of field effect transistors that are the same in thickness of gate insulation film with the thickness of gate insulation film being less than the thickness of the gate insulation film of the first transistor group, and a semiconductor substrate on which the first and second transistor groups are mounted together in a mixed manner, wherein an antenna ratio which is a ratio of the area of a wire to the gate area of a gate electrode is such that the maximum value of the second transistor group is greater than the maximum value of the first transistor group.Type: GrantFiled: July 25, 2008Date of Patent: January 29, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Noriaki Matsunaga, Hitomi Yamaguchi