Abstract: A receiver is operable even if including a local oscillator generating a signal at high frequencies but not in a wide frequency range. The receiver includes: a first frequency converter for mixing a received signal with a first local oscillation signal to convert the received signal into respective signals of plural first intermediate frequencies corresponding to a frequency of the received signal; and a second frequency converter for converting the signals of the first intermediate frequencies into a signal of a second intermediate frequency.

Abstract: A digital signal receiver capable of obtaining a favorable receiving performance even if the input signal level changes rapidly is presented. A control voltage for controlling a variable gain amplifier is read by a microprocessor, and an operation-starting point of the variable gain amplifier is shifted by using this control voltage. As a result, a favorable level fluctuation response characteristic is obtained regardless of the input level.

Abstract: A receiver for a digital broadcasting service have a compatibility between tuning to a desired channel at a short period of time and an improve ment of a bit error rate (BER) characteristics. In a case where a target wave is fluctuated, to prevent the receiver from having a significant declination of BER characteristics and to ensure the reproduction of high quality images, the receiver includes an automatic gain controller including a loop filter in which the frequency range of the loop filter can be switched according to an output of a synchronous state discriminator. The frequency band of the loop filter is selectively adjusted to one setting designed for minimizing the duration for tuning a desired channel before a synchronous state is established. After the synchronous state established, the frequency band of the loop filter is switched to another setting designed for enhancing BER characteristics.

Abstract: A receiver is operable even if including a local oscillator generating a signal at high frequencies but not in a wide frequency range. The receiver includes: a first frequency converter for mixing a received signal with a first local oscillation signal to convert the received signal into respective signals of plural first intermediate frequencies corresponding to a frequency of the received signal; and a second frequency converter for converting the signals of the first intermediate frequencies into a signal of a second intermediate frequency.

Abstract: In a receiver supporting multiple data rates, a sweep control range is calculated on the basis of the data rate of the carrier of the channel to be selected and sweep control is executed on the oscillated frequency by VCO 8 within the sweeping frequency range so that synchronization locking to the carrier is attained and thereby an erroneous channel selection is prevented.

Abstract: The invention presents an apparatus capable of demodulating stably if there are time-course changes in the constituent parts in a demodulator of digital modulated signal. This demodulator comprises an operator for setting the oscillation frequency of a local oscillator 2, and within a passing frequency band of a band pass filter BPF 3, the operator controls the local oscillator 2 so that the frequency of the output signal of a first mixer 1 may settle within a control band in a controllable frequency band of an AFC feedback loop composed of an orthogonal detector 4, a carrier regenerator 9, a frequency error detector 10, a frequency controller 11, a signal selector 12, a D/A converter 13, and a VCO 14, and a local carrier is issued from the local oscillator 2 to the first mixer 1.

Abstract: The invention relates to a filter device, and is intended to prevent drastic changes of output modulation signal and assures the performance as modulator if output modulation signal is transmitted and stopped frequency by using TDMA in communication control. To achieve the object, the invention comprises a shift register 1, a plurality of memories 2 connected to this shift register 1 and increased in the bit width of input address by one bit each, and a selector 3 for selecting outputs from these plurality of memories 2, in which the output of the shift register 1 is used as a higher side address of each one of the memories 2, a lower side address of each one of the memory addresses is common, the bit width of the higher side address increases by one bit each starting from one bit, and addresses are assigned sequentially from the lower side of the higher side address of the memories 2 depending on the shift from the lowest side bit of the shift register 1.

Abstract: A digital signal receiver capable of obtaining a favorable receiving performance even if the input signal level changes rapidly is presented. A control voltage for controlling a variable gain amplifier is read by a microprocessor, and an operation-starting point of the variable gain amplifier is shifted by using this control voltage. As a result, a favorable level fluctuation response characteristic is obtained regardless of the input level.

Abstract: An integrated circuit device is disclosed that comprises a bare integrated circuit chip, having an integrated circuit section and pad sections, said chip being mounted on an insulated surface of a substrate, and an electro-conductive circuit pattern wiring formed on said insulating surface along the periphery of said chip. Tape automated bonding wiring is used to electrically connect the pad sections of the chip to an end of the circuit pattern wiring. Terminals are electrically connected to the other end of the circuit pattern wiring for use in electrically connecting the integrated circuit device to electronic equipment.

Abstract: A plurality of memory modules are stacked so as to form a multilayer integrated memory circuit. All of the memory modules have a plurality of bare memory IC chips mounted thereon, and have the same structure, the same circuit configuration and the same terminal arrangement in lead frames with each other. Each of the memory modules to be stacked in each layer is rotated by 90.degree., 180.degree. or 270.degree. before being stacked and connected to each other. Thus, in the multi-layered memory circuit, it is possible that signals can be selectively input/output to/from a particular layer in the multilayer structure, although the lead terminals of each of memory modules has the same configuration and the same arrangement with each other. As a result, a small-size integrated memory circuit device with a large memory-capacity can be provided, which can be fabricated easily and efficiently. A higher processing speed of digital computers can be also achieved.