Patents by Inventor Hitoo Iwasa
Hitoo Iwasa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8368096Abstract: There are provided image pickup devices capable of significantly increasing production yield and ensuring long-term reliability and a method for manufacturing the image pickup devices.Type: GrantFiled: December 27, 2005Date of Patent: February 5, 2013Assignee: AAC Technologies Japan R&D Center Co., Ltd.Inventors: Osamu Asano, Hitoo Iwasa, Sumio Terakawa, Masami Shouji
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Publication number: 20080042227Abstract: There are provided image pickup devices capable of significantly increasing production yield and ensuring long-term reliability and a method for manufacturing the image pickup devices.Type: ApplicationFiled: December 27, 2005Publication date: February 21, 2008Applicant: I SQUARE RESERCH CO., LTD.Inventors: Osamu Asano, Hitoo Iwasa, Sumio Terakawa, Masami Shouji
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Patent number: 4965644Abstract: Pure-green light emitting diodes include an n-type GaP layer formed on an n-type GaP substrate and a p-type GaP layer formed by using a liquid phase epitaxial method, the average donor concentration of the p-type GaP layer being less than or equal to 5.times.10.sup.16 cm.sup.-3. Liquid phase crystal growth of the above p-type GaP layer is realized by applying a method of keeping the melt used for the liquid phase crystal growth of the n-type GaP layer at a constant temperature and the ambient atmosphere at a reduced pressure for a prescribed period of time thereby to volatilize donor impurities from the melt and to compensate the donor impurities. Pure-green light emitting diodes easily distinguishable from yellow-green and having high brightness can be manufactured by applying the over-compensation method which is suitable for mass production.Type: GrantFiled: November 12, 1985Date of Patent: October 23, 1990Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toshiharu Kawabata, Susumu Koike, Toshio Matsuda, Hitoo Iwasa
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Patent number: 4671829Abstract: In a method of manufacturing pure green light emitting diodes, after an n-type GaP epitaxial layer with thickness larger than or equal to a value for which the density of dislocation on the surface becomes less than or equal to 1.times.10.sup.4 cm.sup.-2 is grown on an n-type GaP substrate, a p-type GaP epitaxial layer is grown on the above n-type epitaxial layer. Even with the use of a GaP substrate with normal dislocation density, the density of dislocation in the neighborhood of the p-n junction becomes low and therefore GaP green light emitting diodes with high intensity of light emission are obtained.Type: GrantFiled: February 22, 1985Date of Patent: June 9, 1987Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toshiharu Kawabata, Susumu Koike, Toshio Matsuda, Hitoo Iwasa
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Patent number: 4354453Abstract: A substrate holder for liquid phase epitaxial growth comprisinga container having a cylindrical space inside thereof, inside wall of said cylindrical space having one or more annular grooves with V-shaped section to hold one or two of said substrates by receiving therein peripheral edges thereof, pitches of said annular grooves being larger than thickness of said one or two substrates,said container having an opening for putting semiconductor solutions into and out of said cylindrical space therethrough and a detachable part for disposing said substrate therethrough;thereby making uniformity of boundary conditions of the peripheries of the semiconductor substrates held in the substrate holder, and hence preventing adverse irregular epitaxial growth at the peripheries.Type: GrantFiled: January 2, 1980Date of Patent: October 19, 1982Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Susumu Koike, Hitoo Iwasa
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Patent number: 4300960Abstract: A method of making a light emitting diode by a liquid phase epitaxial growth is disclosed, the method comprising the steps ofgrowing a first p-type epitaxial layer from a gallium melt containing Zn, and Ga.sub.2 O.sub.3 and GaP on an n-type GaP substrate, or on an n-type epitaxial layer formed on an n-type GaP substrate, at a cooling rate greater than 3.degree. C./min., andgrowing a second p-type epitaxial layer from the gallium melt on the first p-type epitaxial layer at a cooling rate less than 1.5.degree. C./min. This procedure makes the p-type carrier density high at the surface region of the second p-type epitaxial layer and the density of Zn-O pairs high in the first p-type epitaxial layer.Type: GrantFiled: March 18, 1980Date of Patent: November 17, 1981Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Susumu Koike, Hitoo Iwasa
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Patent number: 4268327Abstract: A method for growing semiconductor epitaxial layers for manufacturing semiconductor devices such as light emitting diodes, characterized byusing a single tub for containing a solution comprising solvent solute and additive, andafter growing a first epitaxial layer growth by contacting the solution to a semiconductor substrate, evacuating the space in a container containing said semiconductor substrate and said solution tub, thereby removing at least a part of said additive.Type: GrantFiled: January 7, 1980Date of Patent: May 19, 1981Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tamotsu Uragaki, Morio Inoue, Susumu Koike, Hitoo Iwasa
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Patent number: 4256520Abstract: A method of treating semiconductor substrate comprising the step ofafter epitaxial growth of III-V compound semiconductor layers on a substrate by a liquid phase epitaxial growth method using gallium as solvent,the substrate is treated by an etchant comprising phosphoric acid, acetic acid and nitric acid thereby selectively removing residue stains of gallium on the surface of the substrate.Type: GrantFiled: December 20, 1979Date of Patent: March 17, 1981Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Susumu Koike, Toshio Matsuda, Hitoo Iwasa
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Patent number: 4117587Abstract: A pair of field-effect transistors (hereinafter referred to as FETs) of p-channel type and n-channel type, respectively, both to be electrically actuated in a depletion mode, are formed on a single semiconductor substrate, for instance, a single silicon substrate, and both sources or both drains are connected to each other, or the source of one FET and the drain of the other FET are connected to each other, whereby the pair of FETs are series-connected, and the gate electrode of each FET is connected to the drain electrode or the source electrode that is not series connected in the above-mentioned way, respectively, of the other FET. The device is characterized in that each FET has each back-gate electrode region behind the channel. Preferably, such back-gate regions are high-doped diffused regions.When a voltage of specified range is applied across both non-series-connected electrodes, i.e.Type: GrantFiled: August 6, 1976Date of Patent: October 3, 1978Assignee: Matsushita Electronics CorporationInventors: Gota Kano, Hitoo Iwasa
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Patent number: 4064525Abstract: A pair of field-effect transistors (hereinafter referred to as FETs) of p-channel type and n-channel type, respectively, both to be electrically actuated in a depletion mode, are formed on a single semiconductor substrate, for instance, a single silicon substrate, and both sources or both drains are connected to each other, or the source of one FET and the drain of the other FET are connected to each other, whereby the pair of FETs are series-connected, and the gate electrode of each FET is connected to the drain electrode or the source electrode that is not series connected in the abovementioned way, respectively, of the other FET. When a voltage of specified range is applied across both non-series-connected electrodes, i.e., the two external terminals, the resulting voltage-current characteristic presents a so-called dynatron-type characteristic, producing a negative-resistance phenomenon over a fairly wide range of applied voltage.Type: GrantFiled: June 15, 1976Date of Patent: December 20, 1977Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Gota Kano, Naoyuki Tsuda, Hitoo Iwasa
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Patent number: 3992650Abstract: Across a D.C. power source 1, a load 2, a switching element 4, such as a transistor having a control electrode c (base), and a voltage detection means 5, such as a resistor, are connected in series, and a known negative resistance device 6, having two terminals 31 and 32, is connected by its one terminal 32 to said control electrode c of the switching element 4 and by its other terminal 31 to one end of said series resistor 5 which one end is opposite to that connected to said switching element (4), wherein said negative resistance device 6 comprises, as shown in FIG 2, known complementary connection of a depletion mode n-channel field-effect transistor (FET) and a depletion mode p-channel FET.Type: GrantFiled: January 29, 1975Date of Patent: November 16, 1976Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hitoo Iwasa, Gota Kano
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Patent number: 3991329Abstract: A touch-operation semiconductor switch is constituted by employing a switching device and a semiconductor negative resistance device comprising a complemetary connection of a depletion mode n-channel junction type field-effect transistor (hereinafter: FET) and a depletion mode p-channel junction type FET, both FETs being connected by source to source to each other, and by each gate to each drain of the other FET, and a touching terminal is connected to said common connected sources, so that the on-off state of the negative resistance device is inversed when the touching terminal is touched by human body.Type: GrantFiled: January 31, 1975Date of Patent: November 9, 1976Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hitoo Iwasa, Gota Kano
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Patent number: 3969697Abstract: A series connection comprising a transistor (4) and a light-emitting diode (3) is connected across a D.C. power source (+Vcc), and one end of a negative-resistance device (1) is connected to the base of said transistor (4) and the other end thereof is connected to an end of said light-emitting diode (3), which last-mentioned one end is connected to the D.C. power source (+Vcc). The circuit constituted as above memorizes an occurence of voltage drop which enables bistable switching in the negative-resistance device, thereby energizing the light emitting diode to light. The circuit can be used to indicate voltage lowering or interruption of an A.C. power supply, or weakening of a battery.Type: GrantFiled: December 30, 1974Date of Patent: July 13, 1976Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hitoo Iwasa, Gota Kano
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Patent number: 3937949Abstract: An improvement in optical remote-control apparatus which comprises a light-beam transmitter and a light-receiver, wherein the improvement is that a light-scattering (i.e., light-diffusing) plate having a suitable area is provided in front of the light-receiver, so that the aiming tolerance of the light-beam transmitter becomes broader, enabling easy remote-control.Type: GrantFiled: May 30, 1973Date of Patent: February 10, 1976Assignee: Matsushita Electronics CorporationInventors: Kiyotsugu Ishikawa, Tetsuo Kobune, Hitoo Iwasa, Iwao Teramoto