Patents by Inventor Hitoshi Aida

Hitoshi Aida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240120174
    Abstract: In order to improve the processing reproducibility, an ion milling device 100 includes a sample chamber 107, a sample stage 102 that is disposed in the sample chamber on which a sample is placed, an ion source 101 that emits an unfocused ion beam toward the sample, a control unit 112 that controls an output of the ion beam, an oscillator 104 that is disposed in the sample chamber, and an oscillation circuit 111 that oscillates the oscillator and outputs an oscillation signal to the control unit, in which the control unit controls the output of the ion beam such that a vibrational frequency change amount of the oscillator per unit time due to deposition of sputtered particles generated by irradiating the sample with the ion beam on the oscillator is kept within a predetermined range.
    Type: Application
    Filed: January 22, 2021
    Publication date: April 11, 2024
    Inventors: Shota AIDA, Hisayuki TAKASU, Atsushi KAMINO, Hitoshi KAMOSHIDA
  • Patent number: 6804231
    Abstract: An input distribution packet switch network includes a plurality of 2×2 switch elements and packet input modules for the switch network. The switch elements are arranged in multistage and connected in accordance with Shuffle type topology to constitute a N×N switch network (N=2k, k: integer number of 2 and over). The links of the leftmost and rightmost switch elements are connected to one another so that the N×N switch network can have a ring architecture. The packet input modules are distributed laterally in the switch network.
    Type: Grant
    Filed: September 21, 2000
    Date of Patent: October 12, 2004
    Assignee: The University of Tokyo
    Inventors: Tadao Saito, Hitoshi Aida, Hiroaki Morino, Thai Thach Bao
  • Patent number: 6683872
    Abstract: There is provided a variable rate digital switching system comprising steps of: arranging a plurality of incoming TDM buses and a plurality of sending TDM buses in lattice form; providing cross-point buffers at cross-points of the incoming buses and the sending buses; connecting the cross-point buffers belonging to respective sending TDM buses to respective scheduler; connecting respective contents analyzer to respective scheduler; checking frame headers of input TDM frames by respective cross-point buffers, thereby buffering only data of time slot of destined and belonged sending bus and transmitting contents of the frame header to the contents analyzer; checking the frame header by the contents analyzer, thereby deciding the contents of data stored in the respective cross-point buffers on the own-belonged sending TDM bus, and informing them to the scheduler; performing the scheduling by the scheduler as for how time slots in the sending TDM frame is allocated in respective cross-point buffers according to t
    Type: Grant
    Filed: July 30, 1999
    Date of Patent: January 27, 2004
    Assignee: The University of Tokyo
    Inventors: Tadao Saito, Hitoshi Aida, Terumasa Aoki, Udomkiat Bunworasate
  • Patent number: 6628650
    Abstract: There is provided a variable rate TDM switching system comprising steps of: arranging a plurality of incoming lines and a plurality of sending lines in lattice form; providing time-division gates at cross-points of the incoming lines and the sending lines; connecting time-division temporal switches having a function of transposing the order of time slots in input TDM frames to forward stage of respective incoming lines of the time-division space switches for performing the switching between the incoming lines and the sending lines with time slot unit while holding the multiplexing, by switching these time-division gates; connecting a scheduler for concentratedly controlling the time-division gates and the time-division temporal switches to these gates and time switches; transmitting the headers of the TDM frames to the scheduler in case of inputting the header of TDM frame, and deciding the temporal switching schedule by the scheduler as to the transposition of the order of time slots in the time-division tem
    Type: Grant
    Filed: July 30, 1999
    Date of Patent: September 30, 2003
    Assignee: University of Tokyo
    Inventors: Tadao Saito, Hitoshi Aida, Terumasa Aoki, Soichiro Hidaka, Udomkiat Bunworasate
  • Patent number: 6535557
    Abstract: In a method for coding a moving picture image, in which the moving picture image is coded into a digital moving picture stream when the moving picture image is transmitted via a network, the moving picture image is coded in such a manner that a data unit including a synchronous signal corresponds or conforms to a data transmission unit on the network, or, the moving picture image is coded in such a manner that a synchronous signal is included in a position near a head of respective data transmission units on the network. Therefore, in the digital moving picture stream generated according to the invention, the header of the synchronous layer is included in every maximum length of the IP packet in the variable length packet switching method and in every size of the time slots in the variable bit rate TDM.
    Type: Grant
    Filed: September 7, 1999
    Date of Patent: March 18, 2003
    Assignee: The University of Tokyo
    Inventors: Tadao Saito, Hitoshi Aida, Terumasa Aoki, Takayuki Ohnishi
  • Patent number: 6477173
    Abstract: In a system for switching high-capacity and variable length packets from m input ports to n output ports, k Banyan networks are connected into a ring by means of at least n parallel lines, said input ports are connected to inputs of said Banyan networks in a dispersed manner by means of m input modules, misroute tag check parts are connected to outputs of said Banyan networks as well as to inputs of n output modules whose outputs are connected to said output ports. Each of plural unit switches constituting a Banyan network is constructed such that when an input packet cannot be sent to a desired output, the relevant packet is outputted to a non-occupied output of the relevant Banyan network. When the misroute tag check part finds that the misroute tag is set, the relevant packet is sent to a next stage Banyan network, but when the misroute check tag is not set, the relevant packet is outputted to an output module connected to a desired output.
    Type: Grant
    Filed: September 24, 1998
    Date of Patent: November 5, 2002
    Assignee: The University of Tokyo
    Inventors: Tadao Saito, Hitoshi Aida, Terumasa Aoki