Patents by Inventor Hitoshi Ito
Hitoshi Ito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8536696Abstract: A package substrate including an outermost interlayer resin insulating layer, a pad structure formed on the outermost interlayer resin insulating layer, a conductive connecting pin for establishing an electrical connection with another substrate, the conductive connecting pin being secured to the pad structure via a solder, and via holes formed through the outermost interlayer resin insulating layer and for electrically connecting the pad structure to one or more conductive circuits formed below the outermost interlayer resin insulating layer, the via holes being positioned directly below the pad structure.Type: GrantFiled: August 25, 2009Date of Patent: September 17, 2013Assignee: Ibiden Co., Ltd.Inventors: Naohiro Hirose, Hitoshi Ito, Yoshiyuki Iwata, Masanori Kawade, Hajime Yazu
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Patent number: 8237211Abstract: A non-volatile semiconductor storage device has a memory string including a plurality of electrically rewritable memory cells connected in series. The non-volatile semiconductor storage device also has a protruding layer formed to protrude upward with respect to a substrate. The memory string includes: a plurality of first conductive layers laminated on the substrate; a first semiconductor layer formed to penetrate the plurality of first conductive layers; and an electric charge storage layer formed between the first conductive layers and the first semiconductor layer, and configured to be able to store electric charges. Each of the plurality of first conductive layers includes: a bottom portion extending in parallel to the substrate; and a side portion extending upward with respect to the substrate along the protruding layer at the bottom portion. The protruding layer has a width in a first direction parallel to the substrate that is less than or equal to its length in a lamination direction.Type: GrantFiled: September 9, 2009Date of Patent: August 7, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kito, Hiroyasu Tanaka, Masaru Kidoh, Yosuke Komori, Megumi Ishiduki, Akihiro Nitayama, Hideaki Aochi, Hitoshi Ito, Yasuyuki Matsuoka
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Publication number: 20120032246Abstract: A nonvolatile semiconductor memory device according to an embodiment includes a semiconductor substrate, a memory cell transistor formed in a memory cell region, and a field-effect transistor formed in a peripheral circuit region. The memory cell transistor includes: a floating gate electrode; a first inter-electrode insulating film; and a control gate electrode. The field-effect transistor includes: a lower gate electrode; a second inter-electrode insulating film having an opening; and an upper gate electrode electrically connected to the lower gate electrode via the opening. The control gate electrode and the upper gate electrode are formed by a plurality of conductive films that are stacked. The control gate electrode and the upper gate electrode include a barrier film formed in one of interfaces between the stacked conductive films and configured to suppress diffusion of metal atoms. The control gate electrode and the upper gate electrode have a part that is silicided.Type: ApplicationFiled: August 2, 2011Publication date: February 9, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masashi HONDA, Hitoshi Ito, Hideyuki Kinoshita
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Patent number: 8110917Abstract: A package substrate 310 incorporating a substrate provided with a conductor layer 5, a conductive connecting pin 100 arranged to establish the electrical connection with a motherboard and secured to the surface of the substrate, wherein a pad 16 for securing the conductive connecting pin is provided for the package substrate 310. The pad 16 is covered with an organic resin insulating layer 15 having an opening 18 through which the pad 16 is partially exposed to the outside. The conductive connecting pin 100 is secured to the pad exposed to the outside through the opening with a conductive adhesive agent 17 so that solution of the conductive connecting pin 100 from the substrate occurring, for example when mounting is performed is prevented.Type: GrantFiled: October 19, 2009Date of Patent: February 7, 2012Assignee: IBIDEN Co., Ltd.Inventors: Naohiro Hirose, Hitoshi Ito, Yoshiyuki Iwata, Masanori Kawade, Hajime Yazu
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Patent number: 8105938Abstract: There is provided a method of manufacturing a semiconductor substrate. The method includes: (a) forming a wiring pattern on a substrate; (b) covering the wiring pattern with an insulating resin, thereby forming a first insulating layer; (c) forming a second insulating layer on the first insulating layer; (d) forming a plurality of grooves through the second insulating layer; (e) forming at least one via hole through the first and second insulating layers by irradiating at least one of the grooves with a laser beam; (f) forming a seed metal layer on an inner surface of the at least one via hole, inner surfaces of the grooves, and a surface of the second insulating layer; and (g) forming a plating layer in the at least one via hole and the grooves, by an electrolytic plating using the seed metal layer as a power feeding layer.Type: GrantFiled: May 26, 2009Date of Patent: January 31, 2012Assignee: Shinko Electric Industries Co., Ltd.Inventor: Hitoshi Ito
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Patent number: 8035214Abstract: A package substrate 310 incorporating a substrate provided with a conductor layer 5, a conductive connecting pin 100 arranged to establish the electrical connection with a mother board and secured to the surface of the substrate, wherein a pad 16 for securing the conductive connecting pin is provided for the package substrate 310. The pad 16 is covered with an organic resin insulating layer 15 having an opening 18 through which the pad 16 is partially exposed to the outside. The conductive connecting pin 100 is secured to the pad exposed to the outside through the opening with a conductive adhesive agent 17 so that solution of the conductive connecting pin 100 from the substrate occurring, for example when mounting is performed is prevented.Type: GrantFiled: November 17, 1999Date of Patent: October 11, 2011Assignee: IBIDEN Co., Ltd.Inventors: Naohiro Hirose, Hitoshi Ito, Yoshiyuki Iwata, Masanori Kawade, Hajime Yazu
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Patent number: 8013383Abstract: A nonvolatile semiconductor storage device has a plurality of memory strings in which a plurality of electrically rewritable memory cells are connected in series. The memory string has a columnar semiconductor layer extending in a direction perpendicular to a substrate; a conductive layer formed so as to sandwich a charge storing layer in cooperation with the columnar semiconductor layer; and a metal layer formed so as to be in contact with the top face of the conductive layer.Type: GrantFiled: February 20, 2009Date of Patent: September 6, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Kidoh, Masaru Kito, Ryota Katsumata, Yoshiaki Fukuzumi, Hiroyasu Tanaka, Megumi Ishiduki, Yosuke Komori, Hideaki Aochi, Akihiro Nitayama, Hitoshi Ito, Yasuyuki Matsuoka
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Patent number: 7902659Abstract: A package substrate 310 incorporating a substrate provided with a conductor layer 5, a conductive connecting pin 100 arranged to establish the electrical connection with a mother board and secured to the surface of the substrate, wherein a pad 16 for securing the conductive connecting pin is provided for the package substrate 310. The pad 16 is covered with an organic resin insulating layer 15 having an opening 18 through which the pad 16 is partially exposed to the outside. The conductive connecting pin 100 is secured to the pad exposed to the outside through the opening with a conductive adhesive agent 17 so that solution of the conductive connecting pin 100 from the substrate occurring, for example when mounting is performed is prevented.Type: GrantFiled: January 26, 2009Date of Patent: March 8, 2011Assignee: Ibiden Co., Ltd.Inventors: Naohiro Hirose, Hitoshi Ito, Yoshiyuki Iwata, Masanori Kawade, Hajime Yazu
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Patent number: 7847393Abstract: A package substrate 310 incorporating a substrate provided with a conductor layer 5, a conductive connecting pin 100 arranged to establish the electrical connection with a mother board and secured to the surface of the substrate, wherein a pad 16 for securing the conductive connecting pin is provided for the package substrate 310. The pad 16 is covered with an organic resin insulating layer 15 having an opening 18 through which the pad 16 is partially exposed to the outside. The conductive connecting pin 100 is secured to the pad exposed to the outside through the opening with a conductive adhesive agent 17 so that solution of the conductive connecting pin 100 from the substrate occurring, for example when mounting is performed is prevented.Type: GrantFiled: October 24, 2008Date of Patent: December 7, 2010Assignee: IBIDEN Co., Ltd.Inventors: Naohiro Hirose, Hitoshi Ito, Yoshiyuki Iwata, Masanori Kawade, Hajime Yazu
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Patent number: 7777601Abstract: A movable contacting device in a circuit breaker comprises: a crossbar linked with the opening/closing mechanism and carried so as to pivot cooperatively with the opening/closing mechanism; a movable contact arm engaged, so as to cooperational with the crossbar, with a shaft fitted into a mutually opposing recesses in the crossbar; and a movable contact arm support fixed to the case accomodating the opening/closing mechanism and having mutually opposing through-holes through which the shaft is passed; and the movable contact being configured so that the movable contact slides between surfaces of movable contact arm support having the mutually opposing through-holes; and the construction of a single-pole portion of the movable contact arm is constituted by arranging in parallel two movable contact arm members each having a movable contact at one end, and in a shaft-supporting portion at the other end, an elastic member is sandwiched between the two movable contact arm members.Type: GrantFiled: February 10, 2006Date of Patent: August 17, 2010Assignee: Mitsubishi Electric CorporationInventors: Hiroyuki Kakisako, Hitoshi Ito, Kozo Maeta, Masanori Kawamura, Shigeki Koumoto
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Publication number: 20100096682Abstract: A non-volatile semiconductor storage device has a memory string including a plurality of electrically rewritable memory cells connected in series. The non-volatile semiconductor storage device also has a protruding layer formed to protrude upward with respect to a substrate. The memory string includes: a plurality of first conductive layers laminated on the substrate; a first semiconductor layer formed to penetrate the plurality of first conductive layers; and an electric charge storage layer formed between the first conductive layers and the first semiconductor layer, and configured to be able to store electric charges. Each of the plurality of first conductive layers includes: a bottom portion extending in parallel to the substrate; and a side portion extending upward with respect to the substrate along the protruding layer at the bottom portion. The protruding layer has a width in a first direction parallel to the substrate that is less than or equal to its length in a lamination direction.Type: ApplicationFiled: September 9, 2009Publication date: April 22, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kito, Hiroyasu Tanaka, Masaru Kidoh, Yosuke Komori, Megumi Ishiduki, Akihiro Nitayama, Hideaki Aochi, Hitoshi Ito, Yasuyuki Matsuoka
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Publication number: 20100032200Abstract: A package substrate 310 incorporating a substrate provided with a conductor layer 5, a conductive connecting pin 100 arranged to establish the electrical connection with a motherboard and secured to the surface of the substrate, wherein a pad 16 for securing the conductive connecting pin is provided for the package substrate 310. The pad 16 is covered with an organic resin insulating layer 15 having an opening 18 through which the pad 16 is partially exposed to the outside. The conductive connecting pin 100 is secured to the pad exposed to the outside through the opening with a conductive adhesive agent 17 so that solution of the conductive connecting pin 100 from the substrate occurring, for example when mounting is performed is prevented.Type: ApplicationFiled: October 19, 2009Publication date: February 11, 2010Applicant: IBIDEN CO., LTD.Inventors: Naohiro HIROSE, Hitoshi Ito, Yoshiyuki Iwata, Masanori Kawade, Hajime Yazu
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Publication number: 20090314537Abstract: A package substrate including an outermost interlayer resin insulating layer, a pad structure formed on the outermost interlayer resin insulating layer, a conductive connecting pin for establishing an electrical connection with another substrate, the conductive connecting pin being secured to the pad structure via a solder, and via holes formed through the outermost interlayer resin insulating layer and for electrically connecting the pad structure to one or more conductive circuits formed below the outermost interlayer resin insulating layer, the via holes being positioned directly below the pad structure.Type: ApplicationFiled: August 25, 2009Publication date: December 24, 2009Applicant: IBIDEN CO., LTD.Inventors: Naohiro HIROSE, Hitoshi ITO, Yoshiyuki IWATA, Masanori KAWADE, Hajime YAZU
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Publication number: 20090294979Abstract: There is provided a method of manufacturing a semiconductor substrate. The method includes: (a) forming a wiring pattern on a substrate; (b) covering the wiring pattern with an insulating resin, thereby forming a first insulating layer; (c) forming a second insulating layer on the first insulating layer; (d) forming a plurality of grooves through the second insulating layer; (e) forming at least one via hole through the first and second insulating layers by irradiating at least one of the grooves with a laser beam; (f) forming a seed metal layer on an inner surface of the at least one via hole, inner surfaces of the grooves, and a surface of the second insulating layer; and (g) forming a plating layer in the at least one via hole and the grooves, by an electrolytic plating using the seed metal layer as a power feeding layer.Type: ApplicationFiled: May 26, 2009Publication date: December 3, 2009Applicant: Shinko Electric Industries Co., Ltd.Inventor: Hitoshi Ito
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Publication number: 20090212350Abstract: A nonvolatile semiconductor storage device has a plurality of memory strings in which a plurality of electrically rewritable memory cells are connected in series. The memory string has a columnar semiconductor layer extending in a direction perpendicular to a substrate; a conductive layer formed so as to sandwich a charge storing layer in cooperation with the columnar semiconductor layer; and a metal layer formed so as to be in contact with the top face of the conductive layer.Type: ApplicationFiled: February 20, 2009Publication date: August 27, 2009Applicant: Kabushiki Kaisha ToshibaInventors: Masaru KIDOH, Masaru Kito, Ryota Katsumata, Yoshiaki Fukuzumi, Hiroyasu Tanaka, Megumi Ishiduki, Yosuke Komori, Hideaki Aochi, Akihiro Nitayama, Hitoshi Ito, Yasuyuki Matsuoka
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Publication number: 20090154131Abstract: A package substrate 310 incorporating a substrate provided with a conductor layer 5, a conductive connecting pin 100 arranged to establish the electrical connection with a mother board and secured to the surface of the substrate, wherein a pad 16 for securing the conductive connecting pin is provided for the package substrate 310. The pad 16 is covered with an organic resin insulating layer 15 having an opening 18 through which the pad 16 is partially exposed to the outside. The conductive connecting pin 100 is secured to the pad exposed to the outside through the opening with a conductive adhesive agent 17 so that solution of the conductive connecting pin 100 from the substrate occurring, for example when mounting is performed is prevented.Type: ApplicationFiled: January 26, 2009Publication date: June 18, 2009Applicant: IBIDEN CO., LTD.Inventors: Naohiro HIROSE, Hitoshi ITO, Yoshiyuki IWATA, Masanori KAWADE, Hajime YAZU
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Publication number: 20090053459Abstract: A package substrate 310 incorporating a substrate provided with a conductor layer 5, a conductive connecting pin 100 arranged to establish the electrical connection with a mother board and secured to the surface of the substrate, wherein a pad 16 for securing the conductive connecting pin is provided for the package substrate 310. The pad 16 is covered with an organic resin insulating layer 15 having an opening 18 through which the pad 16 is partially exposed to the outside. The conductive connecting pin 100 is secured to the pad exposed to the outside through the opening with a conductive adhesive agent 17 so that solution of the conductive connecting pin 100 from the substrate occurring, for example when mounting is performed is prevented.Type: ApplicationFiled: October 24, 2008Publication date: February 26, 2009Applicant: IBIDEN CO., LTD.Inventors: Naohiro Hirose, Hitoshi Ito, Yoshiyuki Iwata, Masanori Kawade, Hajime Yazu
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Publication number: 20080289943Abstract: A movable contacting device in a circuit breaker comprises: a crossbar linked with the opening/closing mechanism and carried so as to pivot cooperatively with the opening/closing mechanism; a movable contact arm engaged, so as to cooperational with the crossbar, with a shaft fitted into a mutually opposing recesses in the crossbar; and a movable contact arm support fixed to the case accomodating the opening/closing mechanism and having mutually opposing through-holes through which the shaft is passed; and the movable contact being configured so that the movable contact slides between surfaces of movable contact arm support having the mutually opposing through-holes; and the construction of a single-pole portion of the movable contact arm is constituted by arranging in parallel two movable contact arm members each having a movable contact at one end, and in a shaft-supporting portion at the other end, an elastic member is sandwiched between the two movable contact arm members.Type: ApplicationFiled: February 10, 2006Publication date: November 27, 2008Inventors: Hiroyuki Kakisako, Hitoshi Ito, Kozo Maeta, Masanori Kawamura, Shigeki Koumoto
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Patent number: 7394120Abstract: An MIS transistor includes a gate electrode located to intersect a device region of a semiconductor substrate isolated by a device isolation region, and source and drain regions formed in the semiconductor substrate at both sides of the gate electrode region and elevated source and drain located above the source and drain regions. A gate length of the gate electrode at a boundary between the device isolation region and the device region is longer than the gate length at a central portion of the device region.Type: GrantFiled: June 7, 2005Date of Patent: July 1, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyuki Yamasaki, Hitoshi Ito
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Publication number: 20070231654Abstract: A process of producing a substituted polyacetylene electrolyte membrane which is a solid electrolyte membrane having a sulfonic group uniformly introduced thereinto, with its electrode assembly being useful as an electrochemical device or a fuel cell and an electrolyte membrane using the same are provided. A process of producing a sulfonic group-containing substituted polyacetylene membrane, which includes molding a substituted polyacetylene containing a repeating unit represented by the following formula (1) into a membrane state and bringing the molding into contact with a sulfonating agent to achieve sulfonation and a substituted polyacetylene membrane which is produced by the subject production process and in which the sulfonic group is uniformly distributed in a membrane thickness direction.Type: ApplicationFiled: March 29, 2007Publication date: October 4, 2007Applicant: EBARA CORPORATIONInventors: Hitoshi Ito, Eiichi Akiyama, Hiroshi Yokota, Kazuyoshi Takedai