Abstract: The present invention provides a high-quality semiconductor integrated circuit device, where the semiconductor integrated circuit device, a SiP or especially PoP semiconductor integrated circuit device, enables a simultaneous testing of the reliability of multiple upper and lower semiconductor integrated circuit elements; it also enables a testing of only the non-defective element in case the other is determined defective; moreover, only the defective unit is exchangeable with a non-defective unit. The semiconductor integrated circuit device of the present invention contains multiple semiconductor integrated circuit elements, e.g. semiconductor integrated circuit devices 14 and 16, and a circuit board 12 which relays the respective semiconductor integrated circuit elements 14 and 16, and at least a part of the circuit board 12, e.g.

Abstract: A semiconductor substrate eliminates a restriction caused by a width of scribe lines so as to increase a number of semiconductor elements formed on the semiconductor substrate. A plurality of semiconductor element areas are formed by forming a plurality of unit exposed and printed areas, each of which contains the semiconductor element areas. A first scribe line extends between the semiconductor element areas formed within the unit exposed and printed area. A second scribe line extends between the unit exposed and printed areas. A width of the first scribe line is different from a width of the second scribe line.

Abstract: The present invention provides a high-quality semiconductor integrated circuit device, where the semiconductor integrated circuit device, a SiP or especially PoP semiconductor integrated circuit device, enables a simultaneous testing of the reliability of multiple upper and lower semiconductor integrated circuit elements; it also enables a testing of only the non-defective element in case the other is determined defective; moreover, only the defective unit is exchangeable with a non-defective unit. The semiconductor integrated circuit device of the present invention contains multiple semiconductor integrated circuit elements, e.g. semiconductor integrated circuit devices 14 and 16, and a circuit board 12 which relays the respective semiconductor integrated circuit elements 14 and 16, and at least a part of the circuit board 12, e.g.

Abstract: A burn-in testing method to perform tests with a semiconductor device operated in an atmosphere at a prescribed temperature characterized in that operation instruction signals instructing an operation of the semiconductor device are repeatedly supplied while supplying power to the semiconductor device, and increases and decreases in a power supply current corresponding to the operation instruction signals are counted.

Abstract: A semiconductor substrate eliminates a restriction caused by a width of scribe lines so as to increase a number of semiconductor elements formed on the semiconductor substrate. A plurality of semiconductor element areas are formed by forming a plurality of unit exposed and printed areas, each of which contains the semiconductor element areas. A first scribe line extends between the semiconductor element areas formed within the unit exposed and printed area. A second scribe line extends between the unit exposed and printed areas. A width of the first scribe line is different from a width of the second scribe line.

Abstract: A burn-in testing method to perform tests with a semiconductor device operated in an atmosphere at a prescribed temperature characterized in that operation instruction signals instructing an operation of the semiconductor device are repeatedly supplied while supplying power to the semiconductor device, and increases and decreases in a power supply current corresponding to the operation instruction signals are counted.

Abstract: A burn-in system, a burn-in control technique, and a semiconductor device production method utilizing the burn-in control technique are provided. The burn-in system of the present invention comprises a plurality of burn-in devices and an independent counter terminal. Each of the burn-in devices calculates a parameter indicating the number of mounted semiconductor devices, and generates measurement data indicating quality of the individual semiconductor devices collectively subjected to a burn-in test. The counter terminal adds up the parameters and measurement data sent from the burn-in devices. The counter terminal then calculates a failure rate based on the total parameter and the measurement data, and stops the burn-in test of each of the burn-in devices when the failure rate reaches a predetermined reference value.