Abstract: A power generation unit includes a motor generator having a rotor with magnet, and a stator with coils driven in a plurality of phases, the coils of the respective phases not being connected to each other; and a driving control part that performs control so that a coil of each phase of the stator is brought into any one of a first state in which torque is generated by the rotor, a second state in which both ends of the coil are electrically released, and a third state in which both ends of the coil are short-circuited.

Abstract: A generator motor unit includes a generator motor including a rotor equipped with magnets, and magnetic bodies that protrude from a wall surface, a first stator that makes magnetic flux act on the magnets, thereby generating torque in the rotor, and a second stator that makes magnetic flux act on the magnetic bodies, thereby generating torque in the rotor; and a controller that controls energization of coils of the first stator and the second stator.

Abstract: A power generation unit includes a motor generator having a rotor with magnet, and a stator with coils driven in a plurality of phases, the coils of the respective phases not being connected to each other; and a driving control part that performs control so that a coil of each phase of the stator is brought into any one of a first state in which torque is generated by the rotor, a second state in which both ends of the coil are electrically released, and a third state in which both ends of the coil are short-circuited.

Abstract: A generator motor unit includes a generator motor including a rotor equipped with magnets, and magnetic bodies that protrude from a wall surface, a first stator that makes magnetic flux act on the magnets, thereby generating torque in the rotor, and a second stator that makes magnetic flux act on the magnetic bodies, thereby generating torque in the rotor; and a controller that controls energization of coils of the first stator and the second stator.

Abstract: A circuit designing method includes steps (a) to (d). The step (a) separates a first algorithm description for a simulation into a hardware portion describing hardware and a software portion describing software, and generating a design data automatically, wherein the design data includes behavior data, architecture data, mapping data and address data. The step (b) generates a first clock base description automatically based on the design data, wherein the first clock base description describes relation between the hardware portion and the software portion. The step (c) generates a second clock base description automatically based on the design data, wherein the second clock base description describes the hardware portion. The step (d) generates a first CPU model automatically based on the design data, wherein the first CPU model describes the software portion. Here, the first clock base description, the second clock base description and the first CPU model are used for verifying the design data.

Abstract: An apparatus for estimating power consumption includes an behavioral synthesizing unit and a clock-based simulation unit. The behavioral synthesizing unit is provided with an algorithm-level description as an input and converts the algorithm-level description to a clock-based description and behavioral synthesis information. The clock-based description and behavioral synthesis information are input to the clock-based simulation unit, which proceeds to execute a clock-based simulation and calculates a power consumption factor of a storage element based upon both the clock-based description and behavioral synthesis information.

Abstract: The present invention is used to verify an equivalence between a software for realizing a predetermined function and a hardware data created according to the software and constituting a hardware operating identically as a processing by the software. The LSI verification method of the present invention simulates each of the hardware data and the software and compares, according to a signal I/O condition defining operation of the hardware, an I/O signal state as a simulation result by the hardware data to a software variable as a simulation result of the software for verification of the equivalent.

Abstract: A logic circuit verification device comprising a data input section to read the circuit data and the circuit information of the logic circuits to be verified and converts them into the intermediate format, a corresponding point detection section to extract and output the information about the corresponding points using the corresponding point detection algorithm, a circuit partitioning section to read the intermediate format data and partition the logic circuits according to the corresponding point information obtained by the corresponding point detection section so as to prepare circuit data of the subcircuits and a equivalence checking section to read the circuit data of the subcircuits, determine the subcircuits to be compared with referring to the corresponding point information obtained by the corresponding point detection section and comparatively compares the circuit data of the subcircuits.