Patents by Inventor Hitoshi Ohmichi

Hitoshi Ohmichi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5754061
    Abstract: A Bi-CMOS circuit includes a first bipolar, a second bipolar transistor and a CMOS control unit for performing switching controls of the first and second bipolar transistors on the basis of an input signal applied to an input terminal and for controlling an output signal output via the output terminal on the basis of the input signal. A turn-OFF unit temporality couples the base of the first bipolar transistor to a low-potential side power supply line on the basis of a current flowing in said control means when the first bipolar transistor is turned OFF, so that the first bipolar transistor can be rapidly turned OFF.
    Type: Grant
    Filed: September 3, 1996
    Date of Patent: May 19, 1998
    Assignee: Fujitsu Limited
    Inventors: Shinzou Satou, Kou Ebihara, Akiyoshi Suzuki, Keisuke Ishiwata, Kouji Miki, Hitoshi Ohmichi, Tamio Miyamura, Masamichi Kamiyama
  • Patent number: 4449063
    Abstract: A fundamental logic circuit used, for example, in an electronic computer, comprising an output inverter transistor and a switching transistor which discharges a base charge stored in a storage capacitance in a base-emitter junction of the output inverter transistor when the output inverter transistor changes from the turned on condition to the turned off condition.
    Type: Grant
    Filed: August 22, 1980
    Date of Patent: May 15, 1984
    Assignee: Fujitsu Limited
    Inventors: Hitoshi Ohmichi, Hiromu Enomoto, Yasushi Yasuda, Yoshiharu Mitono, Taketo Imaizumi
  • Patent number: 4388755
    Abstract: A structure and method for manufacturing semiconductor devices by the master slice method, in which various kinds of semiconductor devices are manufactured through utilization of a common master pattern and a plurality of different kinds of selective wiring patterns. A number of bipolar transistors each having plural emitter regions, is formed in a predetermined region, or portion, of a semiconductor substrate by employing a common master pattern, and the plural emitter regions of the respective bipolar transistors are selectively connected by the associated wiring patterns of each thereof to form corresponding bipolar transistors of different, predetermined D.C. characteristics. When manufacturing many different kinds of semiconductor devices by the master slice method, the area which would be wasted on the semiconductor substrate by prior art techniques is greatly reduced, thus providing for enhanced area efficiency.
    Type: Grant
    Filed: November 17, 1980
    Date of Patent: June 21, 1983
    Assignee: Fujitsu Limited
    Inventors: Hiromu Enomoto, Yasushi Yasuda, Yoshiharu Mitono, Taketo Imaizumi, Hitoshi Ohmichi
  • Patent number: 4276556
    Abstract: A semiconductor device including a diode and a bipolar transistor which are connected to each other and formed in an isolated area of a semiconductor layer has a diffused region formed between a base region of the bipolar transistor and a formation region of the diode across the isolated area. The diffused region has the same conductivity type as that of the base region, so that a PNPN diode effect does not occur.
    Type: Grant
    Filed: November 15, 1979
    Date of Patent: June 30, 1981
    Assignee: Fujitsu Limited
    Inventors: Hiromu Enomoto, Yasushi Yasuda, Hitoshi Ohmichi, Yoshiharu Mitono