Patents by Inventor Hitoshi Ota
Hitoshi Ota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240146079Abstract: An electric power tool includes a main body supporting a tool. An electric motor is housed in the main body and configured to drive the tool. A plurality of battery interfaces is integrally formed on the main body, each battery interface having a positive battery terminal and a negative battery terminal. Each battery interface is configured to removably receive a positive battery terminal and a negative battery terminal of a corresponding one of a plurality of battery packs and to electrically connect the plurality of attached battery packs in series with the electric motor. Each of the plurality of battery packs comprises a movable latch configured to engage a corresponding engagement structure defined on or near the corresponding battery interface.Type: ApplicationFiled: January 10, 2024Publication date: May 2, 2024Inventors: Tomoyuki Ota, Kiyoshi Nishibe, Hitoshi Suzuki
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Patent number: 11929036Abstract: An electro-optical device includes: a data signal output circuit including a D/A converter circuit; a plurality of terminals; a control circuit supplied with a power supply potential VL from at least one terminal of the plurality of terminals via a first power supply wiring line; and a power supply circuit configured to generate a power supply potential VPL in accordance with potentials AVDD and AVSS supplied via two or more terminals of the plurality of terminals and supply the power supply potential VPL to a second power supply wiring line. The D/A converter circuit includes a plurality of capacitance elements. The first power supply wiring line or the second power supply wiring line is selectively coupled to one portion of the plurality of capacitance elements.Type: GrantFiled: March 27, 2023Date of Patent: March 12, 2024Assignee: SEIKO EPSON CORPORATIONInventor: Hitoshi Ota
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Publication number: 20240061208Abstract: An optical display device includes an image display element configured to emit image light, a deflection member configured to deflect the image light emitted from the image display element, an optical device including a lens barrel for accommodating a lens group including an objective lens and an eyepiece, and a moving mechanism provided at the lens barrel of the optical device and configured to hold a state in which at least the deflection member is moved in a direction intersecting an optical axis of the lens group.Type: ApplicationFiled: August 17, 2023Publication date: February 22, 2024Applicant: SEIKO EPSON CORPORATIONInventors: Hitoshi OTA, Yuiga HAMADE, Mitsutaka IDE
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Patent number: 11831327Abstract: A DA conversion circuit includes a first DA conversion circuit unit corresponding to a higher bit, a second DA conversion circuit unit corresponding to a lower bit, a capacitance element provided between the first DA conversion circuit unit and the second DA conversion circuit unit, the first DA conversion circuit unit includes a capacitance element and a selection circuit, the second DA conversion circuit unit includes a capacitance element and a selection circuit, and the selection circuit supplies a potential VL or VPH to one end of the capacitance element, and the selection circuit supplies the potential VL or VPL to one end of the capacitance element. The potential VPL is different from the potential VPH, and for example, VPL>VPH.Type: GrantFiled: June 23, 2022Date of Patent: November 28, 2023Assignee: SEIKO EPSON CORPORATIONInventor: Hitoshi Ota
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Patent number: 11800762Abstract: An electro-optical device includes a DA conversion circuit to convert 10 bits of data into an analog voltage output to a data line. The DA conversion circuit includes a first DA conversion circuit to convert upper 5 bits into a voltage and outputs converted voltage to the data line, a second DA conversion circuit to convert lower 5 bits into a voltage and outputs converted voltage to a relay line, and a coupling capacitance including one end electrically coupled to the second DA conversion circuit and another end electrically coupled to the data line, wherein the first DA conversion circuit includes a capacitance element corresponding to the upper 5 bits and is arranged in the Y direction along the data line, and the second DA conversion circuit includes a capacitance element corresponding to the lower 5 bits and is arranged in the Y direction along the data line.Type: GrantFiled: November 4, 2022Date of Patent: October 24, 2023Assignee: SEIKO EPSON CORPORATIONInventor: Hitoshi Ota
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Patent number: 11776486Abstract: A first capacitance element provided corresponding to a bit D0, a second capacitance element provided corresponding to a bit D1, and a third capacitance element and a fourth capacitance element provided corresponding to a bit D2, and electrically coupled in parallel are included. An area S1 where electrodes of the first capacitance element overlap in plan view is smaller than half an area S2 where electrodes of the second capacitance element overlap in plan view, an area in which electrodes of the third capacitance element overlap in plan view is substantially the same as the area S2, and an area where electrodes of the fourth capacitance element overlap in plan view is substantially the same as the area S2.Type: GrantFiled: June 23, 2022Date of Patent: October 3, 2023Assignee: SEIKO EPSON CORPORATIONInventor: Hitoshi Ota
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Patent number: 11776487Abstract: A first capacitance element provided corresponding to a bit D0, a second capacitance element provided corresponding to a bit D1, and a third capacitance element and a fourth capacitance element provided corresponding to a bit D2, and electrically coupled in parallel are included. An area S1 where electrodes of the first capacitance element overlap in plan view is smaller than half an area S2 where electrodes of the second capacitance element overlap in plan view, an area in which electrodes of the third capacitance element overlap in plan view is substantially the same as the area S2, and an area where electrodes of the fourth capacitance element overlap in plan view is substantially the same as the area S2.Type: GrantFiled: November 4, 2022Date of Patent: October 3, 2023Assignee: SEIKO EPSON CORPORATIONInventor: Hitoshi Ota
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Publication number: 20230306915Abstract: An electro-optical device includes: a data signal output circuit including a D/A converter circuit; a plurality of terminals; a control circuit supplied with a power supply potential VL from at least one terminal of the plurality of terminals via a first power supply wiring line; and a power supply circuit configured to generate a power supply potential VPL in accordance with potentials AVDD and AVSS supplied via two or more terminals of the plurality of terminals and supply the power supply potential VPL to a second power supply wiring line. The D/A converter circuit includes a plurality of capacitance elements. The first power supply wiring line or the second power supply wiring line is selectively coupled to one portion of the plurality of capacitance elements.Type: ApplicationFiled: March 27, 2023Publication date: September 28, 2023Applicant: SEIKO EPSON CORPORATIONInventor: Hitoshi OTA
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Publication number: 20230273436Abstract: The display device includes the first light-emitting element, a second light-emitting element, a first color filter through which light from the first light-emitting element passes, and a second color filter through which the light from the second light-emitting element passes. The relative positional relationship between the center of the first light-emitting element and the center of the first color filter is different from the relative positional relationship between the center of the second light-emitting element and the center of the second color filter.Type: ApplicationFiled: May 4, 2023Publication date: August 31, 2023Applicant: SEIKO EPSON CORPORATIONInventors: Takeshi KOSHIHARA, Hitoshi OTA
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Patent number: 11681147Abstract: The display device includes the first light-emitting element, a second light-emitting element, a first color filter through which light from the first light-emitting element passes, and a second color filter through which the light from the second light-emitting element passes. The relative positional relationship between the center of the first light-emitting element and the center of the first color filter is different from the relative positional relationship between the center of the second light-emitting element and the center of the second color filter.Type: GrantFiled: April 29, 2022Date of Patent: June 20, 2023Assignee: SEIKO EPSON CORPORATIONInventors: Takeshi Koshihara, Hitoshi Ota
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Publication number: 20230186855Abstract: A pixel circuit provided corresponding to a scanning line and a data line includes a transistor and an OLED serving as one example of a light emitting element. In a compensation period, a gate node and a drain node of the transistor are electrically coupled to each other to cause a voltage of the gate node of the transistor to be a voltage corresponding to a threshold voltage. In the gate writing period, a voltage of the gate node of the transistor is varied from a voltage corresponding to the threshold voltage into a voltage corresponding to luminance of the OLED, and the voltage corresponding to luminance of the OLED is applied to the drain node of the transistor.Type: ApplicationFiled: December 14, 2022Publication date: June 15, 2023Applicant: SEIKO EPSON CORPORATIONInventors: Takehiko KUBOTA, Hitoshi OTA
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Patent number: 11665928Abstract: An optical module includes a first electro-optical device including a first pixel, a second electro-optical device including a second pixel and a third pixel, and a prism. An area of the second pixel is larger than an area of the first pixel, and an area of the third pixel is smaller than the area of the second pixel. A width of the third pixel in a direction corresponding to a first direction in a synthesized image is not less than 0.5 times and less than 1 time a width of the first pixel in the direction corresponding to the first direction, and a width of the third pixel in a direction corresponding to a second direction in the synthesized image is 0.5 times or more and less than 1 time a width of the first pixel in the direction corresponding to the second direction.Type: GrantFiled: March 28, 2022Date of Patent: May 30, 2023Assignee: SEIKO EPSON CORPORATIONInventors: Hitoshi Ota, Tsuyoshi Tamura, Shinichi Iwata
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Patent number: 11658676Abstract: A DA conversion circuit includes a first DA conversion circuit unit corresponding to a higher bit, a second DA conversion circuit unit corresponding to a lower bit, a capacitance element provided between the first DA conversion circuit unit and the second DA conversion circuit unit, the first DA conversion circuit unit includes a capacitance element and a selection circuit, the second DA conversion circuit unit includes a capacitance element and a selection circuit, and the selection circuit supplies a potential VL or VPH to one end of the capacitance element, and the selection circuit supplies the potential VL or VPL to one end of the capacitance element. The potential VPL is different from the potential VPH, and for example, VPL>VPH.Type: GrantFiled: November 4, 2022Date of Patent: May 23, 2023Assignee: SEIKO EPSON CORPORATIONInventor: Hitoshi Ota
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Publication number: 20230117958Abstract: An electroluminescent device includes a scanning line that extends in a first direction, a light emitting element, a driving transistor that supplies a driving current to the light emitting element, a first conductive layer that is supplied a fixed potential and extends in the first direction, a second conductive layer that is supplied the fixed potential and is disposed on a different layer than the first conductive layer, and a third conductive layer that is electrically connected to a first terminal of the driving transistor and to the light emitting element, and is disposed on a same layer as the second conductive layer. The third conductive layer is surrounded by the second conductive layer in plan view.Type: ApplicationFiled: December 16, 2022Publication date: April 20, 2023Applicant: SEIKO EPSON CORPORATIONInventors: Hitoshi OTA, Ryoichi NOZAWA
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Publication number: 20230094698Abstract: An electro-optical device includes a DA conversion circuit to convert 10 bits of data into an analog voltage output to a data line. The DA conversion circuit includes a first DA conversion circuit to convert upper 5 bits into a voltage and outputs converted voltage to the data line, a second DA conversion circuit to convert lower 5 bits into a voltage and outputs converted voltage to a relay line, and a coupling capacitance including one end electrically coupled to the second DA conversion circuit and another end electrically coupled to the data line, wherein the first DA conversion circuit includes a capacitance element corresponding to the upper 5 bits and is arranged in the Y direction along the data line, and the second DA conversion circuit includes a capacitance element corresponding to the lower 5 bits and is arranged in the Y direction along the data line.Type: ApplicationFiled: November 4, 2022Publication date: March 30, 2023Applicant: SEIKO EPSON CORPORATIONInventor: Hitoshi OTA
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Publication number: 20230069464Abstract: An electro-optical device is provided. The electro optical device includes: a light emitting element configured to emit light according to a current flowing between a pixel electrode and a common electrode; a plurality of power-supply wiring lines provided at a side of the pixel electrode and configured to be supplied with a power source potential; a plurality of data lines; a data-signal outputting circuit configured to output a data signal to a data line; a conductive wiring line provided to overlap with the data-signal outputting circuit in plan view and configured to be supplied with the power source potential through a plurality of mounting terminals, in which each of the plurality of power-supply wiring lines is provided between the plurality of data lines in plan view and electrically coupled to the conductive wiring line.Type: ApplicationFiled: August 29, 2022Publication date: March 2, 2023Applicant: SEIKO EPSON CORPORATIONInventor: Hitoshi OTA
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Publication number: 20230057826Abstract: A first capacitance element provided corresponding to a bit D0, a second capacitance element provided corresponding to a bit D1, and a third capacitance element and a fourth capacitance element provided corresponding to a bit D2, and electrically coupled in parallel are included. An area S1 where electrodes of the first capacitance element overlap in plan view is smaller than half an area S2 where electrodes of the second capacitance element overlap in plan view, an area in which electrodes of the third capacitance element overlap in plan view is substantially the same as the area S2, and an area where electrodes of the fourth capacitance element overlap in plan view is substantially the same as the area S2.Type: ApplicationFiled: November 4, 2022Publication date: February 23, 2023Applicant: SEIKO EPSON CORPORATIONInventor: Hitoshi OTA
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Publication number: 20230055172Abstract: A DA conversion circuit includes a first DA conversion circuit unit corresponding to a higher bit, a second DA conversion circuit unit corresponding to a lower bit, a capacitance element provided between the first DA conversion circuit unit and the second DA conversion circuit unit, the first DA conversion circuit unit includes a capacitance element and a selection circuit, the second DA conversion circuit unit includes a capacitance element and a selection circuit, and the selection circuit supplies a potential VL or VPH to one end of the capacitance element, and the selection circuit supplies the potential VL or VPL to one end of the capacitance element. The potential VPL is different from the potential VPH, and for example, VPL>VPH.Type: ApplicationFiled: November 4, 2022Publication date: February 23, 2023Applicant: SEIKO EPSON CORPORATIONInventor: Hitoshi OTA
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Patent number: 11580907Abstract: An electroluminescent device includes a light-emitting element, a drive transistor that supplies a driving current corresponding to a gradation voltage to the light-emitting element, a first conductive layer that is electrically connected to a gate of the drive transistor, and a second conductive layer that is supplied a fixed potential and that is disposed on a same layer as the first conductive layer. The first conductive layer and the second conductive layer are disposed apart and electrically insulated from one another, and in plan view, the first conductive layer is surrounded by the second conductive layer.Type: GrantFiled: October 20, 2021Date of Patent: February 14, 2023Assignee: SEIKO EPSON CORPORATIONInventors: Hitoshi Ota, Ryoichi Nozawa
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Publication number: 20230044938Abstract: An organic electroluminescent device includes a first transistor, a power supply line layer connected to one current terminal of the first transistor, a capacitive element including a first capacitive electrode connected to a gate of the first transistor, and a second capacitive electrode, a signal line, and a pixel electrode connected to the other current terminal of the first transistor, the first capacitive electrode is provided on a layer over the gate of the first transistor, and the power supply line layer is provided on a layer between the first capacitive electrode and the signal line.Type: ApplicationFiled: October 17, 2022Publication date: February 9, 2023Applicant: SEIKO EPSON CORPORATIONInventors: Hitoshi OTA, Ryoichi NOZAWA