Patents by Inventor Hitoshi Uemura
Hitoshi Uemura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150293427Abstract: An optical modulation device configured of a planar optical waveguide, includes: a light incidence unit which allows light to be incident on the planar optical waveguide; a Mach-Zehnder interferometer which includes a first optical splitter section branching the light incident on the light incidence unit, two arm portions guiding the light branched by the first optical splitter section, a phase modulation unit linearly disposed on each of the two arm portions, and a first optical coupler section combining the light guided from the two arm portions; a light launching unit which launches the light combined by the first optical coupler section from the planar optical waveguide; and a traveling-wave electrode which includes an input unit and an output unit, and applies a voltage to the phase modulation unit.Type: ApplicationFiled: June 24, 2015Publication date: October 15, 2015Applicant: FUJIKURA LTD.Inventors: Kazuhiro GOI, Hiroki ISHIHARA, Kensuke OGAWA, Kenji ODA, Hiroyuki KUSAKA, Ryokichi MATSUMOTO, Hitoshi UEMURA
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Publication number: 20150234120Abstract: An optical device includes: multiple cores each including an inner core and an outer core surrounding an outer circumferential surface of the inner core without any gap therebetween; and cladding surrounding an outer circumferential surface of the cores without any gap therebetween and having a refractive index lower than that of the outer core, wherein each of the cores has a tapered portion that is tapered from one side toward the other side thereof in a longitudinal direction, each of the inner cores includes a low-refractive-index portion, and a high-refractive-index portion surrounding an outer circumferential surface of the low-refractive-index portion without any gap therebetween and having a refractive index higher than that of the low-refractive-index portion, and the outer core has a refractive index lower than that of the high-refractive-index portion.Type: ApplicationFiled: February 10, 2015Publication date: August 20, 2015Applicants: FUJIKURA LTD., NATIONAL UNIVERSITY CORPORATION HOKKAIDO UNIVERSITYInventors: Hitoshi Uemura, Katsuhiro Takenaga, Kunimasa Saitoh
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Patent number: 9069116Abstract: A fan-in/fan-out device includes a plurality of single-core fibers which are connected to a plurality of first cores of a multicore fiber and which include an elongated portion extending in a longitudinal direction so as to reduce a diameter and being connected to a first end portion of the multicore fiber at a second end portion in an extending direction of the elongated portion, where a refractive index distribution of each of the single-core fibers has a single peak, a relative refractive index difference of a second core with respect to a second cladding in each of the single-core fibers is 0.8% or more; and a second mode field diameter of the second end portion of the elongated portion is greater than a first mode field diameter of the first end portion of the multicore fiber.Type: GrantFiled: June 13, 2014Date of Patent: June 30, 2015Assignees: FUJIKURA LTD., National University Corporation Hokkaido UniversityInventors: Hitoshi Uemura, Koji Omichi, Katsuhiro Takenaga, Kunimasa Saitoh
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Publication number: 20140369659Abstract: A fan-in/fan-out device includes a plurality of single-core fibers which are connected to a plurality of first cores of a multicore fiber and which include an elongated portion extending in a longitudinal direction so as to reduce a diameter and being connected to a first end portion of the multicore fiber at a second end portion in an extending direction of the elongated portion, where a refractive index distribution of each of the single-core fibers has a single peak, a relative refractive index difference of a second core with respect to a second cladding in each of the single-core fibers is 0.8% or more; and a second mode field diameter of the second end portion of the elongated portion is greater than a first mode field diameter of the first end portion of the multicore fiber.Type: ApplicationFiled: June 13, 2014Publication date: December 18, 2014Applicants: NATIONAL UNIVERSITY CORPORATION HOKKAIDO UNIV., FUJIKURA LTD.Inventors: Hitoshi UEMURA, Koji OMICHI, Katsuhiro TAKENAGA, Kunimasa SAITOH
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Patent number: 8742474Abstract: A power semiconductor device of the present invention has an active region and an electric field reduction region and includes: an emitter region of a first conductivity type; a base region of a second conductivity type in contact with the emitter region; an electrical strength providing region of the first conductivity type in contact with the base region; a collector region of the second conductivity type in contact with the electrical strength providing region; and a collector electrode in contact with the collector region; wherein the collector region is disposed on both a active region and a electric field reduction region each containing a dopant of the second conductivity type, and the collector region disposed on the electric field reduction region includes a region having a lower density of carriers of the second conductivity type than the collector region disposed on the active region.Type: GrantFiled: November 9, 2007Date of Patent: June 3, 2014Assignee: Mitsubishi Electric CorporationInventors: Yoshiaki Hisamoto, Atsushi Narazaki, Hitoshi Uemura
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Publication number: 20140077259Abstract: A carrier is prevented from being stored in a guard ring region in a semiconductor device. The semiconductor device has an IGBT cell including a base region and an emitter region formed in an n? type drift layer, and a p type collector layer arranged under the drift layer with a buffer layer interposed therebetween. A guard ring region having a guard ring is arranged around the IGBT cell. A lower surface of the guard ring region has a mesa structure provided by removing the collector layer.Type: ApplicationFiled: November 20, 2013Publication date: March 20, 2014Applicant: MITSUBISHI ELECTRIC CORPORATIONInventor: Hitoshi UEMURA
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Patent number: 8643146Abstract: A carrier is prevented from being stored in a guard ring region in a semiconductor device. The semiconductor device has an IGBT cell including a base region and an emitter region formed in an n? type drift layer, and a p type collector layer arranged under the drift layer with a buffer layer interposed therebetween. A guard ring region having a guard ring is arranged around the IGBT cell. A lower surface of the guard ring region has a mesa structure provided by removing the collector layer.Type: GrantFiled: June 13, 2011Date of Patent: February 4, 2014Assignee: Mitsubishi Electric CorporationInventor: Hitoshi Uemura
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Patent number: 8362829Abstract: A semiconductor device includes a power semiconductor array including a first power semiconductor located on one end of the power semiconductor array, a second power semiconductor located on the other end and a third power semiconductor located between the first and second power semiconductors and a diode array including a first diode located on one end of the diode array, a second diode located on the other end and a third diode located between the first and second diodes. A resistance value between an emitter electrode and a collector electrode in ON state is higher at the third power semiconductor than at the first and second power semiconductors. Upon application of a voltage of not less than a rising voltage, the third diode has a higher resistance value than resistance values of the first diode and the second diode upon application of a voltage not less than a rising voltage.Type: GrantFiled: February 24, 2011Date of Patent: January 29, 2013Assignee: Mitsubishi Electric CorporationInventor: Hitoshi Uemura
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Publication number: 20120068310Abstract: A carrier is prevented from being stored in a guard ring region in a semiconductor device. The semiconductor device has an IGBT cell including a base region and an emitter region formed in an n? type drift layer, and a p type collector layer arranged under the drift layer with a buffer layer interposed therebetween. A guard ring region having a guard ring is arranged around the IGBT cell. A lower surface of the guard ring region has a mesa structure provided by removing the collector layer.Type: ApplicationFiled: June 13, 2011Publication date: March 22, 2012Applicant: MITSUBISHI ELECTRIC CORPORATIONInventor: Hitoshi UEMURA
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Publication number: 20110285459Abstract: A semiconductor device includes a power semiconductor array including a first power semiconductor located on one end of the power semiconductor array, a second power semiconductor located on the other end and a third power semiconductor located between the first and second power semiconductors and a diode array including a first diode located on one end of the diode array, a second diode located on the other end and a third diode located between the first and second diodes. A resistance value between an emitter electrode and a collector electrode in ON state is higher at the third power semiconductor than at the first and second power semiconductors. Upon application of a voltage of not less than a rising voltage, the third diode has a higher resistance value than resistance values of the first diode and the second diode upon application of a voltage not less than a rising voltage.Type: ApplicationFiled: February 24, 2011Publication date: November 24, 2011Applicant: MITSUBISHI ELECTRIC CORPORATIONInventor: Hitoshi UEMURA
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Publication number: 20090014753Abstract: A power semiconductor device of the present invention has an active region and an electric field reduction region and includes: an emitter region of a first conductivity type; a base region of a second conductivity type in contact with the emitter region; an electrical strength providing region of the first conductivity type in contact with the base region; a collector region of the second conductivity type in contact with the electrical strength providing region; and a collector electrode in contact with the collector region; wherein the collector region is disposed on both a active region and a electric field reduction region each containing a dopant of the second conductivity type, and the collector region disposed on the electric field reduction region includes a region having a lower density of carriers of the second conductivity type than the collector region disposed on the active region.Type: ApplicationFiled: November 9, 2007Publication date: January 15, 2009Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Yoshiaki Hisamoto, Atsushi Narazaki, Hitoshi Uemura
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Patent number: 5295325Abstract: A plant cutting and transplanting apparatus comprises a plant cutting/transplantation room accommodating a first culture box in which multiplied plants to be cut are planted, and a second culture box in which nodular pieces made by cutting the plants are transplanted; a cutting device adapted to cut, in one lot, the plants in the first culture box to the form of nodular pieces and configured to allow the nodular pieces to rest on the edges thereof, the cutting device being arranged so as to be moved vertically and transversely above the space where the first and second culture boxes are placed; and a blade device having a blade for shaking down the nodular pieces which rest on the cutter and which have been moved to a position above the second culture box.Type: GrantFiled: January 14, 1991Date of Patent: March 22, 1994Assignee: Kabushiki Kaisha Komatsu SeisakushoInventors: Shigeru Honda, Masahiro Sei, Hitoshi Uemura, Tatsuya Mori, Chikaya Sakai, Ruriko Oda, Chiyoko Shimada, Yusaku Sekino
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Patent number: 5209011Abstract: There is disclosed an immature plant grafting apparatus capable of seizing en bloc a plurality of saplings raised in array irrespective of a scatter in diameters of stems without requiring hand works and damaging the saplings and of grafting the saplings at a remarkably high efficiency but at low costs. The grafting apparatus has a plurality of induction plates (9a and 9b) formed with a plurality of induction grooves (10) open to seizing surfaces, corresponding to the number of saplings (3a and 3b) to be seized and their positions, induction plates so attached to upper and lower surfaces of one of a pair of seizing devices (4 and 5) as to protrude from the seizing surfaces, and buffer members (13) projecting from the seizing surfaces of the other seizing device so that each buffer member is fitted in between the pair of induction plates.Type: GrantFiled: September 9, 1991Date of Patent: May 11, 1993Assignee: Kabushiki Kaisha Komatsu SeisakushoInventors: Tatsuya Mori, Masahiro Cei, Shigeru Honda, Hitoshi Uemura, Chikaya Sakai, Ruriko Oda, Chiyoko Shimada, Yusaku Sekino