Abstract: Provided is a data recovery circuit including an input data phase detection circuit for outputting a gate signal synchronized with a rising phase of input data, a gated multiphase oscillator for instantly generating N-phase clocks based on the gate signal as a trigger, data discriminating and reproducing circuits for outputting sampled data of the input data which are synchronized with the clocks, a continuous clock generation circuit for generating a continuous clock which is a reference clock, continuous clock synchronization circuits for synchronizing the sampled data with the continuous clock and outputting the synchronized sampled data as phase synchronization data, and a phase selector for selecting the phase synchronization data having an optimum discrimination phase with the largest phase margin with respect to the input data and outputting the selected phase synchronization data as recovery data.

Abstract: Provided is a data recovery circuit including an input data phase detection circuit for outputting a gate signal synchronized with a rising phase of input data, a gated multiphase oscillator for instantly generating N-phase clocks based on the gate signal as a trigger, data discriminating and reproducing circuits for outputting sampled data of the input data which are synchronized with the clocks, a continuous clock generation circuit for generating a continuous clock which is a reference clock, continuous clock synchronization circuits for synchronizing the sampled data with the continuous clock and outputting the synchronized sampled data as phase synchronization data, and a phase selector for selecting the phase synchronization data having an optimum discrimination phase with the largest phase margin with respect to the input data and outputting the selected phase synchronization data as recovery data.

Abstract: A gain switching circuit switches a conversion gain of a preamplifier that is configured with a series circuit formed with a first resistor and a first switching element and a series circuit formed with a second resistor and a second switching element respectively connected in parallel with a feedback resistor. The gain switching circuit includes a first operating unit that generates a first switching element operating signal for closing the first switching element within a first gain switching period, and a second operating unit that generates a second switching element operating signal for closing the second switching element within a second gain switching period.

Abstract: A frequency divider generates frequency-divided input data by dividing a frequency of input data. A phase comparator detects a phase difference between a phase of a clock generated by a voltage control oscillator and a phase of the frequency-divided input data, and generates a phase difference signal to be used to eliminate the detected phase difference. The voltage control oscillator generates the clock by adjusting an oscillation frequency based on the phase difference signal. A data identifier identifies the input data using the clock generated by the voltage control oscillator.

Abstract: A phase comparator includes: first and second detecting units for detecting an amplitude value of a clock signal at falling timing or rising timing of a data signal; an edge comparing unit for identifying as to whether the first detecting unit detects an amplitude value under a rising state or a falling state to output a first identification result, and for identifying as to whether the second detecting unit detects an amplitude value under a rising state or a falling state to output a second identification result; first and second polarity inverting units for inverting a polarity of output of the first and second detecting units; and a signal selecting unit for selecting one of output values of the first and second polarity inverting units in response to a polarity of the data signal to output the selected output value.

Abstract: A gain switching circuit switches a conversion gain of a preamplifier that is configured with a series circuit formed with a first resistor and a first switching element and a series circuit formed with a second resistor and a second switching element respectively connected in parallel with a feedback resistor. The gain switching circuit includes a first operating unit that generates a first switching element operating signal for closing the first switching element within a first gain switching period, and a second operating unit that generates a second switching element operating signal for closing the second switching element within a second gain switching period.

Abstract: The present invention comprises a phase-locked loop which generates a first clock signal, and a phase-locked loop which generates a second clock signal. An upper limit value of a jitter transmission frequency in the phase-locked loop in which a jitter signal is transmitted to the first clock signal without being suppressed, is not less than an upper limit value of a jitter transmission frequency. An upper limit value of a jitter transmission frequency from the phase-locked loop to the phase-locked loop in which a jitter signal is transmitted to the second clock signal without being suppressed, is not more than an upper limit value of a jitter transmission frequency.

Abstract: A frequency divider generates frequency-divided input data by dividing a frequency of input data. A phase comparator detects a phase difference between a phase of a clock generated by a voltage control oscillator and a phase of the frequency-divided input data, and generates a phase difference signal to be used to eliminate the detected phase difference. The voltage control oscillator generates the clock by adjusting an oscillation frequency based on the phase difference signal. A data identifier identifies the input data using the clock generated by the voltage control oscillator.

Abstract: The polyphase signal generator includes a first delay circuit which adds a first predetermined phase delay to an input signal, a first phase interpolation circuit which generates a first output signal having an output phase prescribed according to a phase difference between the input signal input to one terminal of the first output signal generation unit and a signal input to another terminal of the first output signal generation unit which is output from the delay addition unit, and a second phase interpolation circuit which generates a second output signal having an output phase prescribed according to a phase difference between a signal input to one terminal of the second output signal generation unit which is output from the delay addition unit and an inverted signal of the input signal input to another terminal of the second output signal generation unit.

Abstract: The voltage generator includes the NPN transistor that flows a current corresponding to a voltage VOP output from the error detector. Furthermore, there is provided the current mirror circuit which includes two PNP transistors that flow currents which are multiples of the current that the NPN transistor flows. Furthermore, there are provided two resistors for generating a feedback voltage VFBK to the error detector from an output voltage VREG generated based on a current that the current mirror circuit flows.

Abstract: The present invention comprises a phase-locked loop which generates a first clock signal, and a phase-locked loop which generates a second clock signal. An upper limit value of a jitter transmission frequency in the phase-locked loop in which a jitter signal is transmitted to the first clock signal without being suppressed, is not less than an upper limit value of a jitter transmission frequency. An upper limit value of a jitter transmission frequency from the phase-locked loop to the phase-locked loop in which a jitter signal is transmitted to the second clock signal without being suppressed, is not more than an upper limit value of a jitter transmission frequency.

Abstract: The polyphase signal generator includes a first delay circuit which adds a first predetermined phase delay to an input signal, a first phase interpolation circuit which generates a first output signal having an output phase prescribed according to a phase difference between the input signal input to one terminal of the first output signal generation unit and a signal input to another terminal of the first output signal generation unit which is output from the delay addition unit, and a second phase interpolation circuit which generates a second output signal having an output phase prescribed according to a phase difference between a signal input to one terminal of the second output signal generation unit which is output from the delay addition unit and an inverted signal of the input signal input to another terminal of the second output signal generation unit.

Abstract: The voltage generator includes the NPN transistor that flows a current corresponding to a voltage VOP output from the error detector. Furthermore, there is provided the current mirror circuit which includes two PNP transistors that flow currents which are multiples of the current that the NPN transistor flows. Furthermore, there are provided two resistors for generating a feedback voltage VFBK to the error detector from an output voltage VREG generated based on a current that the current mirror circuit flows.

Abstract: In a clock reproduction and identification device, a clock extraction circuit extracts a transmission line clock from input data and a phase synchronization section reproduces an identification clock synchronized with the transmission line clock in frequency and phase. An identification section identifies the input data based on the identification clock.

Abstract: Voltage controlling/oscillating device comprises a terminal for setting the delay rate in the delay unit and the delay interpolator. Clock signal whose phase is inverted by the inverting gate is inputted into a first input terminal of the delay interpolator and into the delay unit. The delay unit delays the signal by d1 and inputs into second input terminal of the delay interpolator. Oscillation frequency control voltage is fed into a terminal of the delay interpolator through an oscillation frequency control terminal of the device. Delay control voltage is fed into a terminal of the device in order to control a propagation delay rate in the delay unit and the delay interpolator. The delay rate in a delay unit and a delay interpolator can be adjusted by a delay control voltage.