Patents by Inventor Hiu Y. Wong

Hiu Y. Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Tined gate to control threshold voltage in a device formed of materials having piezoelectric properties
    Patent number: 9837523
    Abstract: Roughly described, a field effect transistor has a first piezoelectric layer supporting a channel, a second piezoelectric layer over the first piezoelectric layer, a dielectric layer having a plurality of dielectric segments separated by a plurality of gaps, the dielectric layer over the second piezoelectric layer, and a gate having a main body and a plurality of tines. The main body of the gate covers at least one dielectric segment of the plurality of dielectric segments and at least two gaps of the plurality of gaps. The plurality of tines have proximal ends connected to the main body of the gate, middle portions projecting through the plurality of gaps, and distal ends separated from the first piezoelectric layer by at least the second piezoelectric layer. The dielectric layer exerts stress, creating a piezoelectric charge in the first piezoelectric layer, changing the threshold voltage of the transistor.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: December 5, 2017
    Assignee: Synopsys, Inc.
    Inventors: Hiu Y. Wong, Nelson de Almeida Braga, Rimvydas Mickevicius
  • Tined Gate to Control Threshold Voltage in a Device Formed of Materials Having Piezoelectric Properties
    Publication number: 20170186860
    Abstract: Roughly described, a field effect transistor has a first piezoelectric layer supporting a channel, a second piezoelectric layer over the first piezoelectric layer, a dielectric layer having a plurality of dielectric segments separated by a plurality of gaps, the dielectric layer over the second piezoelectric layer, and a gate having a main body and a plurality of tines. The main body of the gate covers at least one dielectric segment of the plurality of dielectric segments and at least two gaps of the plurality of gaps. The plurality of tines have proximal ends connected to the main body of the gate, middle portions projecting through the plurality of gaps, and distal ends separated from the first piezoelectric layer by at least the second piezoelectric layer. The dielectric layer exerts stress, creating a piezoelectric charge in the first piezoelectric layer, changing the threshold voltage of the transistor.
    Type: Application
    Filed: April 13, 2016
    Publication date: June 29, 2017
    Applicant: Synopsys, Inc.
    Inventors: Hiu Y. Wong, Nelson de Almeida Braga, Rimvydas Mickevicius