Abstract: A reset sub-circuit can sample the reset signal based on a low-speed clock reference signal to generate a series of sampled reset signals. A phase relation between a first selected one of the series of sampled reset signals and the high-speed clock signal at the clock input of each sampler can be measured to generate reset trigger signals corresponding to each of a plurality of samplers. A second selected one of the series of sampled reset signals can be sampled based on the high-speed clock signal to generate a positive sampled reset signal and a negative sampled reset signal. The reset sub-circuit can select between the positive sampled reset signal and the negative sampled reset signal based on the reset trigger signals corresponding to each sampler to generate the synchronous reset signal.

Abstract: A sampling circuitry with a temperature insensitive bandwidth can include a temperature dependent current source, a source-follower amplifier, a storage element and a clocked transmission gate. The source-follower amplifier can be biased by the temperature dependent current source. The source-follower amplifier can be coupled to an input signal node, and the clocked transmission gate can be coupled to a clock signal. The clocked transmission gate can be coupled between an output of the source-follower amplifier and a combination of the storage element and an output signal node. A temperature-based variance in an output impedance of source-follower amplifier, an on-resistance of the clocked transmission gate and the capacitance of the storage element can be substantially cancelled by the temperature dependent current source.

Abstract: A reset sub-circuit can sample the reset signal based on a low-speed clock reference signal to generate a series of sampled reset signals. A phase relation between a first selected one of the series of sampled reset signals and the high-speed clock signal at the clock input of each sampler can be measured to generate reset trigger signals corresponding to each of a plurality of samplers. A second selected one of the series of sampled reset signals can be sampled based on the high-speed clock signal to generate a positive sampled reset signal and a negative sampled reset signal. The reset sub-circuit can select between the positive sampled reset signal and the negative sampled reset signal based on the reset trigger signals corresponding to each sampler to generate the synchronous reset signal.

Abstract: The reset signals output to the lanes of a multi-lane coherent transceiver are synchronized by first synchronizing an asynchronous reset signal to a low-speed clock signal to generate and output a plurality of synchronized reset signals to the lanes. Within each lane, a synchronous reset signal is delayed to generate a number of delayed synchronous reset signals, and the logic states of the synchronous reset signal and the delayed synchronous reset signals are captured. Based on the captured logic states in each of the lanes, a lane synchronized reset signal from the delayed synchronous reset signals is selected for use across all of the lanes.

Abstract: Techniques for correcting clock distortion. The techniques include use of circuitry for detecting and correcting duty cycle distortion and quadrature clock phase distortion. For phase detection, detection circuitry is made simpler and more accurate through the use of a sampling operation in which device mismatch within detection circuitry is accounted for by sampling charge associated with an ideal clock signal across sampling capacitors. When phase detection is performed with the detection circuitry, the stored charge compensates for the device mismatch, improving the accuracy of the detection circuit. The sampling operation is used for duty cycle distortion detection as well. Specifically, a common mode voltage is applied to sampling capacitors, which effectively zeroes the voltage differential between the sampling capacitors, compensating for offset that might exist due to operation of other components of the detection circuit.

Abstract: A clock generator includes: a first input to receive a global clock signal; a second input to receive a completion signal; a third input to receive differential outputs in a conversion cycle from a comparator; and a logic circuit configured to generate a control clock signal based at least in part on the global clock signal and the differential outputs, and to provide the control clock signal to the comparator for a next conversion cycle; and wherein the logic circuit is also configured to disable the control clock signal in response to the completion signal indicating a completion of required conversion cycles in a conversion phase.

Abstract: A circuit for compensating for mismatch in a plurality of channels of a time-interleaved analog-to-digital converter is described. The circuit comprises an analog-to-digital converter circuit of a first channel of the plurality of channels configured to receive an analog input signal and to generate a digital value associated with the analog input signal; an arithmetic circuit configured to receive the digital value generated at the output of the analog-to-digital converter; a memory element configured to receive an output of the arithmetic circuit; and an accumulator circuit coupled to the memory element, wherein the accumulator generates an average value that is provided to the arithmetic circuit to modify the digital value generated at the output of the analog-to-digital converter while receiving the analog input signal.

Abstract: Techniques for correcting clock distortion. The techniques include use of circuitry for detecting and correcting duty cycle distortion and quadrature clock phase distortion. For phase detection, detection circuitry is made simpler and more accurate through the use of a sampling operation in which device mismatch within detection circuitry is accounted for by sampling charge associated with an ideal clock signal across sampling capacitors. When phase detection is performed with the detection circuitry, the stored charge compensates for the device mismatch, improving the accuracy of the detection circuit. The sampling operation is used for duty cycle distortion detection as well. Specifically, a common mode voltage is applied to sampling capacitors, which effectively zeroes the voltage differential between the sampling capacitors, compensating for offset that might exist due to operation of other components of the detection circuit.

Abstract: A circuit for implementing a time-interleaved analog-to-digital converter is described. The circuit comprises a sampling clock generator configured to receive a reference clock signal having a first frequency.

Abstract: An analog-to-digital converter circuit is described.