Abstract: A scan rate controller includes a write phase lock loop for generating a write clock signal, a read timing generator for generating a fixed read timing clock signal, and a frame memory for storing a video signal according to the write clock signal from the write phase lock loop and a write timing clock signal from a timing generator, and outputting the video signal according to the read timing clock signal from read timing generator, thereby converting an image size in accordance with various video modes into an image size corresponding to a fixed video mode.

Abstract: A flat panel display apparatus includes a sampling clock generator for generating a sampling clock signal with a frequency corresponding to a synchronous signal supplied from a host, a phase detector for detecting the phase difference between the sampling clock signal and the synchronous signal to generate a phase difference data, a comparator for comparing the phase difference data with a delay data corresponding to the synchronous signal to generate a correction signal, a micro-controller for generating the delay data and for increasing or decreasing the frequency divisional value of the sampling clock generator to adjust the frequency of the sampling clock signal in response to the correction signal, and an analog to digital converter for converting an analog video signal into corresponding digital video signal in response to the sampling clock signal.

Abstract: A flat panel display apparatus includes a sampling clock generator for generating a sampling clock signal with a frequency corresponding to a synchronous signal supplied from a host, a delay circuit for delaying the sampling clock signal, a level converter for converting an analog video signal supplied from the host to have a given digital voltage level, a phase detector for detecting the phase difference between the digital voltage level video signal from the level converter and the sampling clock signal delayed by the delay circuit to generate a phase difference data, a comparator for comparing the phase difference data with a delay data corresponding to the synchronous signal, a micro-controller for generating the delay data to increase or decrease the delay time of the delay circuit to adjust the phase of the sampling clock signal in response to the output of the comparator, and an analog to digital converter for converting the analog video signal into corresponding digital video signal in response to the

Abstract: A display includes: a clock signal generator for generating a first sampling clock signal used for converting an analog video signal supplied from a host to a digital video signal; a tracking control circuit for generating tracking control data corresponding to a tracking adjustment key input; an A/D converter for converting the analog video signal to the digital video signal in synchronism with a second clock signal obtained by delaying the first sampling clock signal according to the tracking control data; a high frequency clock signal generator for generating a high frequency clock signal, and the tracking control circuit measuring the presently delayed time of the second sampling clock signal by means of the high frequency clock signal so as to adjust the delayed time according to the tracking control data.

Abstract: A format converter includes: a microcomputer for receiving horizontal and vertical synchronizing signals from a host, determining a video mode, and generating data that indicates the number of dots per a period of a horizontal output signal; a W-PLL and time generator for receiving the data from the microcomputer, and generating a write clock signal; an R-PLL and time generator for receiving the data and the horizontal synchronizing signal respectively generated by the microcomputer and the host, and generating a read clock signal; an AD converting section for sampling an analog picture signal received from the host according to the write clock signal of the W-PLL and time generator, and converting it to a digital picture signal; and a format converting section for storing the picture signal received from the AD converter according to the period of the write clock signal of the W-PLL and time generator, and converting the format of the stored picture signal according to the read clock signal received from the

Abstract: A pseudo-synchronizing signal generator for use in a digital image processing apparatus is disclosed.

Abstract: A device for controlling an aspect ratio in a TV-computer integrated wide screen receiver, includes an input signal select switch for selecting a television signal double-scanned or a computer monitor signal of a VGA mode, a gain controller for controlling a gain of the signal which is selected by the select switch, a clamp circuit for clamping the signal controlled by the gain controller, an analog/digital converter for converting the signal clamped by the clamp circuit, an aspect ratio conversion device for horizontally and vertically converting the digital signal sampled by the analog/digital converter; and a phase-locked loop connected to the analog/digital converter and the aspect ratio conversion device, for correcting an image distortion by controlling a converting clock speed.

Abstract: An image size adjusting apparatus for a digital display monitor using a liquid crystal display (LCD) panel includes a frequency multiplier circuit having a programmable divider, and six line memories in which two line memories are designated per each color picture signal line. The adjustment of the horizontal size of the display image can be achieved by changing the amount of sampling data in cooperation with the PLL circuit and the programmable divider. Also, adjustment of the vertical size can be achieved by changing the number of scanning lines such that double scanning is performed during one period of the horizontal synchronization signals, using the line memories. Thus, the apparatus provides for a simplification of adjusting operations of the horizontal and vertical image size of a digital display monitor.

Abstract: A raster controller having a microprocessor for storing a preset video signal of red, green and blue components, a clock generator for generating a clock signal of a constant time period, a synchronization and blocking signal generator for receiving a clock signal output from the clock generator and a video signal output from a microprocessor so as to generate a synchronization signal and a blanking signal, a multiplexer for inputting a synchronizing signal generated from the synchronization and blanking signal generator and a horizontal synchronizing signal supplied from a video signal generator in a computer system, responsive to a raster control signal, and for selectively generating a synchronization signal, an AND gate for inputting a blanking signal output from the synchronization and blanking signal generator to perform a logic product operation and a switch, responsive to the raster control signal, for inputting a signal output from the AND gate so as to switch on/off a video signal output.

Abstract: An oscillation and trigger circuit for a vertical synchronizing signal in a display apparatus, the oscillation and trigger circuit comprising: a pulse generator for generating a single pulse for each active cycle of the vertical synchronizing signal; a first signal detector having an input terminal connected to an output terminal of the pulse generator, for determining a state of no input of the vertical synchronizing signal whose frequency is less than a predetermined frequency and for generating a first predetermined signal indicative of the state; a second signal detector having input terminals connected to respective output terminals of the pulse generator and the first signal detector, for checking a time interval of the vertical synchronizing signal input to the pulse generator so as to output a second predetermined signal when the time interval exceeds a predetermined time period and for outputting the second predetermined signal responsive to the first predetermined signal input from the first signal

Abstract: A power control circuit of a monitor capable of being applied to all kinds of monitors is constructed to supply a control signal in accordance with the state of the monitor among On, Stand-by, Suspend and Off states by considering the input of vertical and horizontal sync signals after checking the current input state of the horizontal and vertical sync signals of the monitor, thereby facilitating the embodiment of the circuit that provides the control signal according to the current power supply state of the monitor by an ASIC.