Abstract: An input/output (I/O) circuit may be provided. The I/O circuit may include an input control circuit and an output control circuit. The input control circuit may be configured to apply a stress to a transmission path based on an input signal while in a test mode and buffer the input signal using a drivability changed by the stress applied to the transmission path to generate first and second transmission signals while in a normal mode after the test mode. The output control circuit may be configured to drive and output an output signal according to the first and second transmission signals based on a test mode signal.

Abstract: An input/output (I/O) circuit may be provided. The I/O circuit may include an input control circuit and an output control circuit. The input control circuit may be configured to apply a stress to a transmission path based on an input signal while in a test mode and buffer the input signal using a drivability changed by the stress applied to the transmission path to generate first and second transmission signals while in a normal mode after the test mode. The output control circuit may be configured to drive and output an output signal according to the first and second transmission signals based on a test mode signal.

Abstract: An input/output (I/O) circuit may be provided. The I/O circuit may include an input control circuit and an output control circuit. The input control circuit may be configured to apply a stress to a transmission path based on an input signal while in a test mode and buffer the input signal using a drivability changed by the stress applied to the transmission path to generate first and second transmission signals while in a normal mode after the test mode. The output control circuit may be configured to drive and output an output signal according to the first and second transmission signals based on a test mode signal.

Abstract: A semiconductor apparatus may include a unit memory region, a first column main decoder, a second column main decoder, and a control circuit. The unit memory region may include a plurality of sub-memory regions. The first and second column main decoders may be configured to receive and decode a column pre-decoding signal and configured to generate a respective column select signal for controlling a column access of a respective first and second half of the plurality of sub-memory regions. The control circuit may be configured to provide the column pre-decoding signal to the first or second column main decoders based on their proximities to a sub-memory region to be enabled among the plurality of sub-memory regions.

Abstract: A semiconductor apparatus may include a unit memory region, a first column main decoder, a second column main decoder, and a control circuit. The unit memory region may include a plurality of sub-memory regions. The first and second column main decoders may be configured to receive and decode a column pre-decoding signal and configured to generate a respective column select signal for controlling a column access of a respective first and second half of the plurality of sub-memory regions. The control circuit may be configured to provide the column pre-decoding signal to the first or second column main decoders based on their proximities to a sub-memory region to be enabled among the plurality of sub-memory regions.

Abstract: A semiconductor device includes a package interface including N numbers of first group of data balls which are disposed on a first side thereof, N numbers of second group of data balls which are disposed on a second side thereof, and M numbers of command/address balls which are disposed between the first side and the second side; a first semiconductor chip which is stacked on the first side over the package interface, and includes 2N numbers of first group of data pads and M numbers of first command/address pads; and a second semiconductor chip which is stacked on the second side over the package interface, and includes 2N numbers of second group of data pads and M numbers of second command/address pads.

Abstract: A degradation detection circuit may include a degradation unit including multiple delay elements driven by a high voltage for degradation. The high voltage for degradation value may be higher than an operation voltage. The degradation unit may be configured to provide a first delayed signal after passing a test signal through the degradation unit, wherein the test signal retains a pulse for a preset time. The degradation detection circuit may include a reference unit including a plurality of delay elements driven by the operation voltage, and configured to provide a second delayed signal after passing the test signal through the reference unit, a delay setting unit configured to provide a third delayed signal by selectively adding delay elements with respect to the second delayed signal, and a delay checking logic configured to detect a delay of the test signal by comparing the first delayed signal and the third delayed signal.

Abstract: An input/output (I/O) circuit may be provided. The I/O circuit may include an input control circuit and an output control circuit. The input control circuit may be configured to apply a stress to a transmission path based on an input signal while in a test mode and buffer the input signal using a drivability changed by the stress applied to the transmission path to generate first and second transmission signals while in a normal mode after the test mode. The output control circuit may be configured to drive and output an output signal according to the first and second transmission signals based on a test mode signal.

Abstract: A semiconductor device may include a driving control signal generation circuit configured to generate a driving control signal by determining whether a corresponding operation is a gapless read operation, according to a read strobe signal. The semiconductor device may also include a power driving circuit configured to drive a supply voltage to a power supply voltage in response to the driving control signal, and a read control signal generation circuit configured to generate a read control signal for controlling a read operation from the read strobe signal in response to the supply voltage.

Abstract: A degradation detection circuit may include a degradation unit including multiple delay elements driven by a high voltage for degradation. The high voltage for degradation value may be higher than an operation voltage. The degradation unit may be configured to provide a first delayed signal after passing a test signal through the degradation unit, wherein the test signal retains a pulse for a preset time. The degradation detection circuit may include a reference unit including a plurality of delay elements driven by the operation voltage, and configured to provide a second delayed signal after passing the test signal through the reference unit, a delay setting unit configured to provide a third delayed signal by selectively adding delay elements with respect to the second delayed signal, and a delay checking logic configured to detect a delay of the test signal by comparing the first delayed signal and the third delayed signal.

Abstract: A semiconductor device that includes: a detection circuit suitable for detecting a gapless pattern section of a detection target signal; and an internal circuit suitable for performing a normal operation during a normal section and additionally performing the normal operation during a compensating section corresponding to the gapless pattern section in response to a detection result signal outputted from the detection circuit.

Abstract: A semiconductor device includes a package interface including N numbers of first group of data balls which are disposed on a first side thereof, N numbers of second group of data balls which are disposed on a second side thereof, and M numbers of command/address balls which are disposed between the first side and the second side; a first semiconductor chip which is stacked on the first side over the package interface, and includes 2N numbers of first group of data pads and M numbers of first command/address pads; and a second semiconductor chip which is stacked on the second side over the package interface, and includes 2N numbers of second group of data pads and M numbers of second command/address pads.

Abstract: A semiconductor device that includes: a detection circuit suitable for detecting a gapless pattern section of a detection target signal; and an internal circuit suitable for performing a normal operation during a normal section and additionally performing the normal operation during a compensating section corresponding to the gapless pattern section in response to a detection result signal outputted from the detection circuit.

Abstract: The semiconductor device includes a comparator and a data output unit. The comparator compares a phase of a first pulse signal generated in a first memory region with a phase of a second pulse signal generated in a second memory region and responsively generates a detection signal. The data output unit outputs first data received from the first memory region as output data in synchronization with a first output strobe signal generated by defining a pulse width of a first strobe signal in response to the detection signal and outputs second data received from the second memory region as the output data in synchronization with a second output strobe signal generated by defining a pulse width of a second strobe signal in response to the detection signal.

Abstract: The semiconductor device includes a comparator and a data output unit. The comparator compares a phase of a first pulse signal generated in a first memory region with a phase of a second pulse signal generated in a second memory region and responsively generates a detection signal. The data output unit outputs first data received from the first memory region as output data in synchronization with a first output strobe signal generated by defining a pulse width of a first strobe signal in response to the detection signal and outputs second data received from the second memory region as the output data in synchronization with a second output strobe signal generated by defining a pulse width of a second strobe signal in response to the detection signal.

Abstract: A semiconductor integrated circuit includes a first ground voltage pad, a second ground voltage pad, an internal voltage generation unit, and a division unit. The first ground voltage pad is configured to receive a first ground voltage. The second ground voltage pad is configured to receive a second ground voltage. The internal voltage generation unit includes a comparison unit configured to compare a reference voltage with a feedback voltage by using the first ground voltage, and a driving unit configured to drive an internal voltage terminal in response to an output signal of the comparison unit. The division unit is coupled between the internal voltage terminal and the second ground voltage pad, and configured to divide a voltage of the internal voltage pad and generate the feedback voltage supplied to the internal voltage generation unit.

Abstract: A semiconductor integrated circuit includes a first ground voltage pad, a second ground voltage pad, an internal voltage generation unit, and a division unit. The first ground voltage pad is configured to receive a first ground voltage. The second ground voltage pad is configured to receive a second ground voltage. The internal voltage generation unit includes a comparison unit configured to compare a reference voltage with a feedback voltage by using the first ground voltage, and a driving unit configured to drive an internal voltage terminal in response to an output signal of the comparison unit. The division unit is coupled between the internal voltage terminal and the second ground voltage pad, and configured to divide a voltage of the internal voltage pad and generate the feedback voltage supplied to the internal voltage generation unit.

Abstract: An internal voltage generator of a semiconductor integrated circuit includes a comparison unit configured to compare a reference voltage with a feedback voltage, a driving unit configured to drive an internal voltage terminal in response to an output signal of the comparison unit, and a feedback unit configured to divide a voltage of the internal voltage terminal according to a division ratio adjustable in response to a control signal and output a division voltage as the feedback voltage.

Abstract: A semiconductor device includes a monitor voltage transfer unit and a voltage generating unit. The monitor voltage transfer unit selects one of a plurality of internal voltages including a cell plate voltage in accordance with a test mode to output it to a voltage monitor pad or outputs an external voltage supplied from the voltage monitor pad as a first pre cell plate voltage. The voltage generating unit generates the cell plate voltage using any one of the first pre cell plate voltage and a second pre cell plate voltage generated within itself in accordance with the test mode. The semiconductor device can generate a pre cell plate voltage at the desired level.

Abstract: A semiconductor memory device which prevents a drop of the level of an external voltage due to generation of high voltage, thereby ensuring an effective data window. The semiconductor memory device includes a level detecting unit and a voltage generating unit. The level detecting unit is configured to detect a level of an internal voltage based on a reference voltage to output a level detection signal. The voltage generating unit is configured to generate the internal voltage by selectively pumping an external voltage according to the level detection signal and a refresh signal.