Abstract: A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.

Abstract: A method and apparatus to manufacture a flip chip package includes dotting a flux on a first preliminary bump of a package substrate, attaching a preliminary bump of a first semiconductor chip to the first preliminary bump of the package substrate via the flux, dotting a flux on a second preliminary bump of the package substrate, and attaching a preliminary bump of a second semiconductor chip to the second preliminary bump of the package substrate via the flux. Accordingly, an evaporation of the flux on the preliminary bump of the package substrate may be suppressed.

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.

Abstract: A method of forming a semiconductor package having a large capacity and a reduced or minimized volume includes: attaching a semiconductor substrate on a support substrate using an adhesive layer, wherein the semiconductor substrate includes a plurality of first semiconductor chips and a chip cutting region, wherein first and second ones of the plurality of first semiconductor chips are separated each other by the chip cutting region, and the semiconductor substrate includes a first surface on which an active area is formed and a second surface opposite to the first surface; forming a first cutting groove having a first kerf width, between the first and second ones of the plurality of first semiconductor chips, so that the semiconductor substrate is separated into a plurality of first semiconductor chips; attaching a plurality of second semiconductor chips corresponding to the first semiconductor chips, respectively, to the plurality of first semiconductor chips; forming a molding layer so as to fill the first

Abstract: A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.

Abstract: Provided are a double-sided adhesive tape, semiconductor packages, and methods of fabricating the packages. A method of fabricating semiconductor packages includes providing a double-sided adhesive tape on a top surface of a carrier, the double-sided adhesive tape including a first adhesive layer and a second adhesive layer stacked on the first adhesive layer, the first adhesive layer of the double-sided adhesive tape being in contact with the top surface of the carrier, adhering active surfaces of a plurality of semiconductor chips onto the second adhesive layer of the double-sided adhesive tape, separating the first adhesive layer from the second adhesive layer such that the second adhesive layer remains on the active surfaces of the semiconductor chips, patterning the second adhesive layer to form first openings that selectively expose the active surfaces of the semiconductor chips, and forming first conductive components on the second adhesive layer to fill the first openings.

Abstract: To manufacture a stack semiconductor package, a board mold covers a first semiconductor. The board mold includes a first face and a second face opposite to the first face. An active surface of the first semiconductor faces the second face. A first opening is formed in the board mold from the second surface. The first opening is disposed on the first semiconductor. A second opening penetrates the board mold from the first surface. A conductive metal layer fills the first and the second openings using an electroless plating method. A plurality of semiconductor devices is stacked on the first face of the board mold.

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.

Abstract: A semiconductor apparatus having a through electrode, a semiconductor package, and a method of manufacturing the semiconductor package are provided. The method of includes preparing a substrate including a buried via, the buried via having a first surface at a first end, and the buried via extending from a first substrate surface of the substrate into the substrate; planarizing a second substrate surface of the substrate opposite the first substrate surface to form a through via by exposing a second via surface at a second end of the buried via opposite the first end; forming a conductive capping layer on the exposed second via surface of the through via; and recessing the second substrate surface so that at least a first portion of the through via extends beyond the second substrate surface.

Abstract: Provided is a semiconductor package including a first semiconductor chip and a second semiconductor chip respectively disposed at a bottom and at a top so that active surfaces thereof face each other. Further includes is a first molding member for sealing the first semiconductor chip and exposing the active surface of the first semiconductor chip through a top surface, a first rewiring formed on the top surface of the first molding member and the active surface of the first semiconductor chip, a second rewiring formed on a bottom surface of the first molding member, a through-via for penetrating through the first molding member and electrically connecting the first and second rewirings, and a first connection member disposed between the first and second semiconductor chips. Also provided are various systems including same and various methods for making same.

Abstract: A method of forming a semiconductor package having a large capacity and a reduced or minimized volume includes: attaching a semiconductor substrate on a support substrate using an adhesive layer, wherein the semiconductor substrate includes a plurality of first semiconductor chips and a chip cutting region, wherein first and second ones of the plurality of first semiconductor chips are separated each other by the chip cutting region, and the semiconductor substrate includes a first surface on which an active area is formed and a second surface opposite to the first surface; forming a first cutting groove having a first kerf width, between the first and second ones of the plurality of first semiconductor chips, so that the semiconductor substrate is separated into a plurality of first semiconductor chips; attaching a plurality of second semiconductor chips corresponding to the first semiconductor chips, respectively, to the plurality of first semiconductor chips; forming a molding layer so as to fill the first

Abstract: A semiconductor chip and a first heat dissipation pattern are mounted on a substrate. The first heat dissipation pattern has an opening therein and exposes the semiconductor chip therethrough. A second heat dissipation pattern including a thermal interface material (TIM) is interposed between a side surface of the semiconductor chip and the first heat dissipation pattern.

Abstract: A method of forming a semiconductor package includes attaching a semiconductor substrate on a support substrate, wherein the semiconductor substrate includes a plurality of first semiconductor chips and a chip cutting region that separates respective ones of the semiconductor chips. A first cutting groove is formed that has a first kerf width between first and second ones of the plurality of first semiconductor chips. A plurality of second semiconductor chips is attached to the plurality of first semiconductor chips. A molding layer is formed so as to fill the first cutting groove and a second cutting groove having a second kerf width that is less than the first kerf width is formed in the molding layer so as to form individual molding layers covering one of the plurality of first semiconductor chips and one of the plurality of second semiconductor chips.

Abstract: A method of manufacturing semiconductor chips includes providing a semiconductor substrate including circuit regions, irradiating the semiconductor substrate with a laser beam onto to form a frangible layer, and polishing the semiconductor substrate to separate the circuit regions of the semiconductor substrate from one another into semiconductor chips. The frangible layer may be removed completely during the polishing of the semiconductor substrate.

Abstract: A method of molding a semiconductor package includes coating liquid molding resin or disposing solid molding resin on a top surface of a semiconductor chip arranged on a substrate. The solid molding resin may include powdered molding resin or sheet-type molding resin. In a case where liquid molding resin is coated on the top surface of the semiconductor chip, the substrate is mounted between a lower molding and an upper molding, and then melted molding resin is filled in a space between the lower molding and the upper molding. In a case where the solid molding resin is disposed on the top surface of the semiconductor chip, the substrate is mounted on a lower mold and then the solid molding resin is heated and melts into liquid molding resin having flowability. An upper mold is mounted on the lower mold, and melted molding resin is filled in a space between the lower molding and the upper molding.

Abstract: A method of fabricating a semiconductor device includes preparing a semiconductor substrate having a circuit unit on an upper surface thereof, a metal pad electrically connected to the circuit unit, and a passivation layer that covers the circuit unit and exposes the metal pad, forming a first re-wiring layer that is electrically connected to the metal pad and is formed by a printing method to extend from the metal pad on the passivation layer and forming a second re-wiring layer on the first re-wiring layer using the first re-wiring layer as a seed by using an electro-plating process.

Abstract: A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.

Abstract: A debonder to manufacture a semiconductor that includes: a stage to support a carrier wafer that is attached to a chip stack assembly by a temporary adhesive layer coated on the surface of the carrier wafer; a chuck arranged above the stage to selectively secure the chip stack assembly; a lifting unit to lift the chuck from the stage; a lateral driving unit to move the chuck laterally with respect to the stage; and a controller to control the lifting unit and the lateral driving unit.

Abstract: A semiconductor package and method of manufacturing thereof are provided. The package includes: a substrate; a first metal wire on a top surface of the substrate; a first semiconductor chip disposed on the substrate; a first insulation layer which covers the first semiconductor chip and at least a part of the substrate; a second metal wire formed on a top surface of the first insulation layer; a first via formed in the first insulation layer, wherein the first via electrically connects the second metal wire and the first metal wire; and a second semiconductor chip disposed on the second metal wire, wherein the second semiconductor chip is electrically connected to the second metal wire.

Abstract: A semiconductor device includes a first device including a first substrate and a first external connection terminal for connecting outside the first device; a second device stacked on the first device, the second device including a second substrate and a second external connection terminal for connecting outside the second device; an adhesive pattern disposed between the first device and second device, the adhesive pattern disposed in locations other than locations where the first external connection terminal and second external connection terminal are disposed, and the adhesive pattern causing the first device and second device, when stacked, to be spaced apart by a predetermined distance; and a plated layer disposed between and electrically and physically connecting the first external connection terminal and the second external connection terminal.