Patents by Inventor Hojun SEONG
Hojun SEONG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240015970Abstract: Disclosed is a semiconductor memory device comprising a second substrate on a first substrate and including a lower semiconductor layer and an upper semiconductor layer on the lower semiconductor layer, an electrode structure on the upper semiconductor layer and including a plurality of stacked electrodes, a vertical channel structure that penetrates the electrode structure and is connected to the second substrate, an interlayer dielectric layer that covers the electrode structure, and a cutting structure that penetrates the interlayer dielectric layer and the upper semiconductor layer. The upper semiconductor layer has a first sidewall defined by the cutting structure. The lower semiconductor layer has a second sidewall adjacent to the first sidewall. The first sidewall and the second sidewall are horizontally offset from each other.Type: ApplicationFiled: September 26, 2023Publication date: January 11, 2024Inventors: Woosung Yang, HOJUN SEONG, JOONHEE LEE, JOON-SUNG LIM, EUNTAEK JUNG
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Patent number: 11792982Abstract: Disclosed is a semiconductor memory device comprising a second substrate on a first substrate and including a lower semiconductor layer and an upper semiconductor layer on the lower semiconductor layer, an electrode structure on the upper semiconductor layer and including a plurality of stacked electrodes, a vertical channel structure that penetrates the electrode structure and is connected to the second substrate, an interlayer dielectric layer that covers the electrode structure, and a cutting structure that penetrates the interlayer dielectric layer and the upper semiconductor layer. The upper semiconductor layer has a first sidewall defined by the cutting structure. The lower semiconductor layer has a second sidewall adjacent to the first sidewall. The first sidewall and the second sidewall are horizontally offset from each other.Type: GrantFiled: September 21, 2020Date of Patent: October 17, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Woosung Yang, Hojun Seong, Joonhee Lee, Joon-Sung Lim, Euntaek Jung
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Publication number: 20220367511Abstract: A three-dimensional semiconductor memory device may include a source structure on a substrate, a stack structure including electrode layers and inter-electrode insulating layers, which are on the source structure and are alternately stacked, a vertical structure penetrating the stack structure and the source structure and being adjacent to the substrate, and a separation insulation pattern penetrating the stack structure and the source structure and being spaced apart from the vertical structure. The uppermost one of the inter-electrode insulating layers may include a first impurity injection region located at a first height from a top surface of the substrate. The stack structure may define a groove, in which the separation insulation pattern is located. An inner sidewall of the groove may define a recess region, which is located at the first height from the top surface of the substrate and is recessed toward the vertical structure.Type: ApplicationFiled: April 26, 2022Publication date: November 17, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Younjeong HWANG, Minbum KIM, Hojun SEONG, Sung-Hun LEE, Juneon JIN
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Publication number: 20210225870Abstract: Disclosed is a semiconductor memory device comprising a second substrate on a first substrate and including a lower semiconductor layer and an upper semiconductor layer on the lower semiconductor layer, an electrode structure on the upper semiconductor layer and including a plurality of stacked electrodes, a vertical channel structure that penetrates the electrode structure and is connected to the second substrate, an interlayer dielectric layer that covers the electrode structure, and a cutting structure that penetrates the interlayer dielectric layer and the upper semiconductor layer. The upper semiconductor layer has a first sidewall defined by the cutting structure. The lower semiconductor layer has a second sidewall adjacent to the first sidewall. The first sidewall and the second sidewall are horizontally offset from each other.Type: ApplicationFiled: September 21, 2020Publication date: July 22, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: WOOSUNG YANG, HOJUN SEONG, JOONHEE LEE, JOON-SUNG LIM, EUNTAEK JUNG
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Patent number: 9997525Abstract: A semiconductor device may include a first conductive pattern having a line portion and a pad portion connected to the line portion on a substrate, a gate insulating pattern and a second conductive pattern sequentially stacked on the substrate, and a capping layer disposed on the first and second conductive patterns. A first trench is defined in an upper portion of the substrate adjacent to one side of the second conductive pattern, and the capping layer at least partially fills the first trench.Type: GrantFiled: January 4, 2017Date of Patent: June 12, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-Hwang Sim, Hojun Seong, Bongtae Park, Woo-Jung Kim
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Patent number: 9773795Abstract: Disclosed are non-volatile memory devices and methods of manufacturing the same. The non-volatile memory device includes device isolation patterns defining active portions in a substrate and gate structures disposed on the substrate. The active portions are spaced apart from each other in a first direction and extend in a second direction perpendicular to the first direction. The gate structures are spaced apart from each other in the second direction and extend in the first direction. Each of the device isolation patterns includes a first air gap, and each of a top surface and a bottom surface of the first air gap has a wave-shape in a cross-sectional view taken along the second direction.Type: GrantFiled: April 21, 2015Date of Patent: September 26, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Hwang Sim, Jinhyun Shin, HoJun Seong
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Publication number: 20170221755Abstract: A semiconductor device may include a first conductive pattern having a line portion and a pad portion connected to the line portion on a substrate, a gate insulating pattern and a second conductive pattern sequentially stacked on the substrate, and a capping layer disposed on the first and second conductive patterns. A first trench is defined in an upper portion of the substrate adjacent to one side of the second conductive pattern, and the capping layer at least partially fills the first trench.Type: ApplicationFiled: January 4, 2017Publication date: August 3, 2017Inventors: Jae-Hwang SIM, Hojun SEONG, Bongtae PARK, Woo-Jung KIM
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Patent number: 9508551Abstract: A method of fabricating a semiconductor device includes stacking an etch target layer, a first mask layer, and a second mask layer on a first surface of a substrate. A plurality of first spacer lines are formed parallel to each other and a first spacer pad line on the second mask layer is formed. A third mask pad in contact with at least the first spacer pad line on the second mask layer is formed. The second mask layer and the first mask layer are etched to form one or more first mask lines, a first mask preliminary pad, and second mask patterns. Second spacer lines are respectively formed covering sidewalls of the first mask preliminary pad and the first mask lines. First mask pads are formed. The etch target layer is etched to form conductive lines and conductive pads connected to the conductive lines.Type: GrantFiled: March 23, 2015Date of Patent: November 29, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hojun Seong, Jae-Hwang Sim, Jeehoon Han
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Publication number: 20150325478Abstract: A method of fabricating a semiconductor device includes stacking an etch target layer, a first mask layer, and a second mask layer on a first surface of a substrate. A plurality of first spacer lines are formed parallel to each other and a first spacer pad line on the second mask layer is formed. A third mask pad in contact with at least the first spacer pad line on the second mask layer is formed. The second mask layer and the first mask layer are etched to form one or more first mask lines, a first mask preliminary pad, and second mask patterns. Second spacer lines are respectively formed covering sidewalls of the first mask preliminary pad and the first mask lines. First mask pads are formed. The etch target layer is etched to form conductive lines and conductive pads connected to the conductive lines.Type: ApplicationFiled: March 23, 2015Publication date: November 12, 2015Inventors: Hojun SEONG, Jae-Hwang SIM, Jeehoon HAN
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Publication number: 20150228660Abstract: Disclosed are non-volatile memory devices and methods of manufacturing the same. The non-volatile memory device includes device isolation patterns defining active portions in a substrate and gate structures disposed on the substrate. The active portions are spaced apart from each other in a first direction and extend in a second direction perpendicular to the first direction. The gate structures are spaced apart from each other in the second direction and extend in the first direction. Each of the device isolation patterns includes a first air gap, and each of a top surface and a bottom surface of the first air gap has a wave-shape in a cross-sectional view taken along the second direction.Type: ApplicationFiled: April 21, 2015Publication date: August 13, 2015Inventors: Jae-Hwang Sim, Jinhyun Shin, HoJun Seong
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Patent number: 9041088Abstract: Disclosed are non-volatile memory devices and methods of manufacturing the same. The non-volatile memory device includes device isolation patterns defining active portions in a substrate and gate structures disposed on the substrate. The active portions are spaced apart from each other in a first direction and extend in a second direction perpendicular to the first direction. The gate structures are spaced apart from each other in the second direction and extend in the first direction. Each of the device isolation patterns includes a first air gap, and each of a top surface and a bottom surface of the first air gap has a wave-shape in a cross-sectional view taken along the second direction.Type: GrantFiled: July 24, 2014Date of Patent: May 26, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Hwang Sim, Jinhyun Shin, HoJun Seong
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Patent number: 8975684Abstract: Disclosed are non-volatile memory devices and methods of manufacturing the same. The non-volatile memory device includes device isolation patterns defining active portions in a substrate and gate structures disposed on the substrate. The active portions are spaced apart from each other in a first direction and extend in a second direction perpendicular to the first direction. The gate structures are spaced apart from each other in the second direction and extend in the first direction. Each of the device isolation patterns includes a first air gap, and each of a top surface and a bottom surface of the first air gap has a wave-shape in a cross-sectional view taken along the second direction.Type: GrantFiled: June 11, 2013Date of Patent: March 10, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Hwang Sim, Jinhyun Shin, HoJun Seong
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Publication number: 20140332894Abstract: Disclosed are non-volatile memory devices and methods of manufacturing the same. The non-volatile memory device includes device isolation patterns defining active portions in a substrate and gate structures disposed on the substrate. The active portions are spaced apart from each other in a first direction and extend in a second direction perpendicular to the first direction. The gate structures are spaced apart from each other in the second direction and extend in the first direction. Each of the device isolation patterns includes a first air gap, and each of a top surface and a bottom surface of the first air gap has a wave-shape in a cross-sectional view taken along the second direction.Type: ApplicationFiled: July 24, 2014Publication date: November 13, 2014Inventors: Jae-Hwang Sim, Jinhyun Shin, HoJun Seong
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Publication number: 20140021524Abstract: Disclosed are non-volatile memory devices and methods of manufacturing the same. The non-volatile memory device includes device isolation patterns defining active portions in a substrate and gate structures disposed on the substrate. The active portions are spaced apart from each other in a first direction and extend in a second direction perpendicular to the first direction. The gate structures are spaced apart from each other in the second direction and extend in the first direction. Each of the device isolation patterns includes a first air gap, and each of a top surface and a bottom surface of the first air gap has a wave-shape in a cross-sectional view taken along the second direction.Type: ApplicationFiled: June 11, 2013Publication date: January 23, 2014Inventors: Jae-Hwang Sim, Jinhyun Shin, HoJun Seong
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Publication number: 20120058639Abstract: A method of forming a nonvolatile memory device includes providing conductive pillars disposed in a first insulating layer and disposed on a semiconductor substrate, providing an etch stop layer on the first insulating layer, disposing a mold layer on the etch stop layer, and forming grooves in the mold layer. The grooves respectively extend over the conductive pillars in a first direction. The method further includes patterning the etch stop layer using the grooves to form holes respectively corresponding to the conductive pillars, and filling a metal into the grooves and the holes. The metal in the holes contacts the conductive pillars.Type: ApplicationFiled: July 29, 2011Publication date: March 8, 2012Inventors: Jae-Hwang SIM, Jong-Min LEE, Hojun SEONG